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FPGA utilization #98

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podhrmic opened this issue Mar 4, 2022 · 1 comment
Open

FPGA utilization #98

podhrmic opened this issue Mar 4, 2022 · 1 comment
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hardware software Someday Issues that are not required by our current contract, but we'd like to attend to someday. WiP
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@podhrmic
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podhrmic commented Mar 4, 2022

For a simple firmware with a small-footprint printf:

#include <stdint.h>
//#include <stdio.h>
#include "bsp.h"
#include "printf.h"

#define GPIO_REG 0x01000000

int main(void)
{
    volatile uint32_t *gpio = (void*) GPIO_REG;
    uint32_t cnt = 0;
    printf("Hello world\n");
    while(1) {
        printf("%u miliseconds passed\n",time_in_ms());
        *gpio = cnt;
        cnt++;
        delay_ms(1000);
    }

    return 0;
}

I get .text section of size 22kB.

As a result fixing:

  • imem at 24kB.
  • dmem at 4kB which is barely enough for a tiny stack/heap and .data section.

Resulting utilization:

Info: Device utilisation:
Info: 	       TRELLIS_SLICE: 23649/41820    56%
Info: 	          TRELLIS_IO:    91/  365    24%
Info: 	                DCCA:     1/   56     1%
Info: 	              DP16KD:    49/  208    23%
Info: 	          MULT18X18D:     0/  156     0%
Info: 	              ALU54B:     0/   78     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  224     0%
Info: 	            SIOLOGIC:     0/  141     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   14     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%

Synthesis time: 26min

@podhrmic
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podhrmic commented Mar 5, 2022

With dmem being 8kB (more reasonable) I am getting:

Info: Device utilisation:
Info: 	       TRELLIS_SLICE: 32701/41820    78%
Info: 	          TRELLIS_IO:    91/  365    24%
Info: 	                DCCA:     1/   56     1%
Info: 	              DP16KD:    49/  208    23%
Info: 	          MULT18X18D:     0/  156     0%
Info: 	              ALU54B:     0/   78     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  224     0%
Info: 	            SIOLOGIC:     0/  141     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   14     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%

@kiniry kiniry added this to the Task 4: Presentation milestone Mar 7, 2022
@kiniry kiniry added the Someday Issues that are not required by our current contract, but we'd like to attend to someday. label Oct 28, 2022
@kiniry kiniry removed this from the Task 4: Presentation milestone Oct 28, 2022
@kiniry kiniry added this to the FPGA milestone May 22, 2023
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