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Add autoformatting of FPGA verilog files #297

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npetersen2 opened this issue May 4, 2023 · 0 comments

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npetersen2 commented May 4, 2023

The formatting of the verilog files leaves a bit to be desired... At a minimum, there are pretty bad tab/space issues.

We already autoformat the C code, why not the verilog code?

At first pass, there is not a standard formatter people seem to use, so we'll have to find a suitable one.

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