Testing multiple interrupts from FPGA, different priorities, preemption, etc

[npetersen2]

Verify that interrupts are working.

• the interrupt signal (sched_isr) is being asserted as per FPGA logic and at the correct time
• test basic interrupt on CPU 0 (set manually)
• test basic interrupt on CPU 1 (set manually)
• the interrupt is calling the handler (isr0) after scheduler
• enable the second interrupt and test that can also be sent at a lower/high priority

[annikaolson]

After looking at some online resources and discussing on the 2/27 meeting, we realized the issue was very likely dual-core related.

I tried running it on CPU 0 - with the basic interrupt that is manually set (i.e. interrupt = slv_reg0 and have a test_int() function in timing_manager.c that sets slv_reg0 to 1) - and that called the ISR.

Edit:

Tested the same interrupt on CPU, used the following function & arguments: XScuGic_InterruptMaptoCpu(intc_instance_ptr, 1, INTC_INTERRUPT_ID_1);

Success!

[annikaolson]

Current issue:

While I can now get an interrupt generated on CPU 1, I noticed that the ISR for the sched_isr interrupt (the one that is actually used) was still not being called... I tested the basic interrupt before and after the scheduler is initialized:

And the ISR is no longer called.
this post looks to be a very similar situation (private timer interrupts and 2 PL-PS interrupts)

[annikaolson]

Got it working, but I had to initialize the timing manager (and thus the PL-PS interrupts) after the scheduler - I put a print statement in the scheduler isr to see if that was still being called, and it is - so this might work? it might just be more efficient to put everything in one function, though

[annikaolson]