integrating both L2 cache miss counter and throttle #58
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Hi, I do not understand what you mean by "how can i integrate" You want to throttle a core accessing L2, based on cache miss he does on L2 ? If so, you only need to modify the Cache.scala.
Yes
This is for the cache to send read requests to the DDR. (L2 cache refill) |
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One thing about the L2 cache design, is that it has a "replay queue" which could be used to easily throttle a specific core requests. It is controlled by https://github.com/SpinalHDL/SpinalHDL/blob/dev/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala#L630C11-L630C18 , see the various condition at which this flag is set |
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So You would then need to generate a proper givenCpuThrottle which depend on the CTRL_CMD.source |
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as givenCpuThrottle comes from cache miss counter or from a memory-mapped counter How can I throttle specific core based on per Miss counter, which is equivalent to givenCpuThrottle? How to supply givenCpuThrottle into /src/main/scala/spinal/lib/bus/tilelink/coherent/cache.scala from https://github.com/SpinalHDL/NaxSoftware/blob/8927ab57bb5b7f531d1c58fe96417bae2a264144/baremetal/socdemo/src/crt.S |
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How do you want to connect the counter to a bit ? |
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Previously i did so I incremented the counter by +1 as long as there is cache miss in every cycle. i used later that counter to create some algorithm for throttling the CPU core |
Dolu1990
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Oct 31, 2023
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Here is an example of per CPU throttle :
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Then remains to add a control bus port to the l2 to make that throtteling configurable. |
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Thank you so much. Will it be possible to merge to the main branch of git because when I compile i just copied the necessary updated part of code and get some errors?
val missCost = 200 Instead of writing the misscost value manually 200, can we read the actual value? I mean |
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Got it configurable: Using https://github.com/SpinalHDL/NaxRiscv/tree/throttle_l2 And that assembly code : |
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thank you can you please tell me how you compile (all steps please) the files which are in different git branch ? How is it possible to see in gtkwaves also ? |
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you just need the NaxRiscv throttle_l2 branch cloned in a recursive manner, it include the SpinalHDL as a git module. i did my test using opening the sbt shell in NaxRiscv and then |
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Thank you so much :) i am curious how can i get play.elf file when i run compile myself |
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Should be good with cd ext/NaxSoftware/baremetal/play
replace src/crt.S content with that assembly code snippet
make rv32ima |
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sbt "runMain naxriscv.Gen64" && make -C src/test/cpp/naxriscv compile can we do it by staying main branch in NaxRiscv and in dev branch in spainalHDL ? |
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no, SpinalHDL main is only for releases and is behind why switching branches to something else than throttle_l2 ? |
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ok i stay in throttle_l2 in Main hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_throttle_branch/NaxRiscv$ git branch -a
but which branch to stay in SpinalHDL hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_throttle_branch/NaxRiscv/ext/SpinalHDL$ git branch -a
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I get some errors by git checkout throttle_l2 |
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Same as specified by the git submodule. i just did : All went fine can you try aswell from a fresh clone ? |
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Thank you so much 🙏 🙏 How to use play.elf where we can find files to load in GTK waves ? & which file is it (e.g. VCD) ? seems like .fst but couldnot find it The error message suggests that the program is unable to locate the "iverilog-vpi" file, resulting in a "No such file or directory" error. This is likely causing the Java exception and the subsequent failure of the program to run. i have following files I get following errors |
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Hi, ahhh the crash you had is because the sim was configured to use icarus verilog instead of verilator.
That's an executable, you can give it to SoCSim via --load-elf play.elf arguement, it will load it
Will be in NaxRiscv/simWorkspace/SocDemo/test.fst |
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still i face errors |
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Which version of verilator do you have ? |
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mine is Verilator 4.038 2020-07-11 rev v4.036-114-g0cd4a57ad kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/simWorkspace/SocDemo$ verilator --version |
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Ahhh that's tooo old |
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i updated it and later i get another problem now i have Verilator 4.216 2021-12-05 rev v4.216 |
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Ahh that's when ext/rvls isn't compiled. So either you can build ext/rvls, either you use --no-rvls argument (never tested) |
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I did so sbt:NaxRiscv> runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf play.elf --trace --nax-count 2 --no-rvls did i did correctly ? |
can't find play.elf |
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now it seems working Should it be look like this ? I feel it might be stuck somewhere how run in litex -->> FPGA ? |
yes ^^ The SocSim isn't using the same SoC than litex. but it isn't much different I guess with that special branch, l2.cache.ctrl at 0x20000 of bus is missing in NaxSoc |
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Next day i again try to run again and i did following i first run sbt server then then but i face some errors Do you also get such errors ? what can be cause of this errors [error] Exception in thread "main" java.lang.NullPointerException |
Will it be possible to update in following spinal.lib.bus.tilelink.coherent.CacheParam && spinal.lib.bus.tilelink.coherent.CacheFiber so It could run in Litex ? Thank you so much i get some errors like this The first error seems to suggest that throttleList is not recognized as a member of CacheParam, and the second error indicates that ctrl is not recognized as a member of CacheFiber. |
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With f3a21af ? |
what is the issue with [error] Exception in thread "main" java.lang.NullPointerException |
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What is SocSim.scala:172 on your codebase ? |
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Ahh with --no-rvls i can reproduce. |
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I am wondering how can i integrate these both part of code which are in different location
NaxRiscv/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala
https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala#L113
SpinalHDL/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala
https://github.com/SpinalHDL/SpinalHDL/blob/1f8a2fc205deed991a4d1e63795b6b43003a9b90/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala#L1063
I guess writing address 0xF30 wont be ok writing inside coherent/Cache.scala along with l2.cache
This part of code
scope.add( )(memory mapped variable counter ) is very important for Bandwidth regulation.Another Question
Will it be possible to throttle specific core from L2 cache in case there is too many miss happening from specific core of multicore?
I guess this is for whole L2 cache ( blocking accessing data for shared L2 cache )
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