threshold of maxiumum count of Naxcore that can be possible to simulate ?

[SoCScholar]

Do i have to update in following code of naxRiscv/ext/NaxSoftware/baremetal/socdemo/crt.s

if i need multicore refill and writeback value

instead of multiplying with ""0*0x80""

#define SCOPE_HART0 (SCOPE + 0*0x80)

Do i need to multiply with maschine hard id (mhartid) csrr x1, mhartid

#define SCOPE 0x14000000
#define SCOPE_L2_AQUIRE_MISS (SCOPE + 0xF04)
#define SCOPE_L2_GETPUT_MISS (SCOPE + 0xF24)
#define SCOPE_HART0 (SCOPE + i*0x80)  // according to number of core 
#define SCOPE_HART_DCACHE_REFILL 0x10


   //read SCOPE_HART0_DCACHE_REFILL
    //la x1, SCOPE_HART0 + SCOPE_HART_DCACHE_REFILL

    li x20, 0x14000000
    li x2, 0x80
    csrr x1, mhartid
    slli x1, x1, 4 // i 
    mul x1, x1, x2  // i * 0x80  
    addi x1, x1, x20 // x1== i * 0x80   + 0x14000000 
    addi x1, x1, SCOPE_HART_DCACHE_REFILL // x1==   i * 0x80   + 0x14000000 + 0x10 
    lw x10, 0(x1)

what is the maximum count of Nax that be possible to simulate ?

I tried with 20, it worked but when i tried with 200, it failed

sbt:NaxRiscv> runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf play.elf --trace --nax-count 200 --no-rvls

sbt:NaxRiscv> runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf play.elf --trace --nax-count 200 --no-rvls
[info] running (fork) naxriscv.platform.tilelinkdemo.SocSim --load-elf play.elf --trace --nax-count 200 --no-rvls
[info] [Runtime] SpinalHDL dev    git head : 3f9c287705429bbc0182cc415f187fc3e6b8eeeb
[info] [Runtime] JVM max memory : 7960.0MiB
[info] [Runtime] Current date : 2023.11.06 20:03:23
[info] [Progress] at 0.000 : Elaborate components
[info] **********************************************************************************************
[info] [Warning] Elaboration failed (0 error).
[info]           Spinal will restart with scala trace to help you to find the problem.
[info] **********************************************************************************************
[info] [Progress] at 85.420 : Elaborate components
[error] Exception in thread "main" java.lang.AssertionError: assertion failed: BusSlaveFactory DOUBLE-READ-ERROR : bit 0 of bus address 3840 should be written by scope_fiber_naxes_30_thread_core_FetchCachePlugin_logic_refill_fire_counter but it is already occupied by another signal at the same address!
[error] 	at scala.Predef$.assert(Predef.scala:170)
[error] 	at spinal.core.package$.assert(core.scala:500)
[error] 	at spinal.lib.bus.misc.BusSlaveFactoryDelayed$$anonfun$1$$anonfun$apply$mcV$sp$6$$anonfun$apply$7$$anonfun$apply$4.apply$mcVI$sp(BusSlaveFactory.scala:801)
[error] 	at spinal.lib.bus.misc.BusSlaveFactoryDelayed$$anonfun$1$$anonfun$apply$mcV$sp$6$$anonfun$apply$7$$anonfun$apply$4.apply(BusSlaveFactory.scala:800)
[error] 	at spinal.lib.bus.misc.BusSlaveFactoryDelayed$$anonfun$1$$anonfun$apply$mcV$sp$6$$anonfun$apply$7$$anonfun$apply$4.apply(BusSlaveFactory.scala:800)
[error] 	at scala.collection.immutable.List.foreach(List.scala:392)
[error] 	at spinal.lib.bus.misc.BusSlaveFactoryDelayed$$anonfun$1$$anonfun$apply$mcV$sp$6$$anonfun$apply$7.apply(BusSlaveFactory.scala:800)
[error] 	at spinal.lib.bus.misc.BusSlaveFactoryDelayed$$anonfun$1$$anonfun$apply$mcV$sp$6$$anonfun$apply$7.apply(BusSlaveFactory.scala:797)
[error] 	at scala.collection.TraversableLike$WithFilter$$anonfun$foreach$1.apply(TraversableLike.scala:733)
[error] 	at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error] 	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error] 	at scala.collection.TraversableLike$WithFilter.foreach(TraversableLike.scala:732)
[error] 	at spinal.lib.bus.misc.BusSlaveFactoryDelayed$$anonfun$1$$anonfun$apply$mcV$sp$6.apply(BusSlaveFactory.scala:797)
[error] 	at spinal.lib.bus.misc.BusSlaveFactoryDelayed$$anonfun$1$$anonfun$apply$mcV$sp$6.apply(BusSlaveFactory.scala:795)
[error] 	at scala.collection.TraversableLike$WithFilter$$anonfun$foreach$1.apply(TraversableLike.scala:733)
[error] 	at scala.collection.mutable.LinkedHashMap.foreach(LinkedHashMap.scala:141)
[error] 	at scala.collection.TraversableLike$WithFilter.foreach(TraversableLike.scala:732)
[error] 	at spinal.lib.bus.misc.BusSlaveFactoryDelayed$$anonfun$1.apply$mcV$sp(BusSlaveFactory.scala:795)
[error] 	at spinal.core.Component$$anonfun$prePop$1.apply(Component.scala:180)
[error] 	at spinal.core.Component$$anonfun$prePop$1.apply(Component.scala:178)
[error] 	at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error] 	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error] 	at spinal.core.Component.prePop(Component.scala:178)
[error] 	at spinal.core.fiber.EngineContext$$anonfun$start$1$$anonfun$apply$1.apply$mcV$sp(AsyncCtrl.scala:79)
[error] 	at spinal.core.fiber.EngineContext$$anonfun$start$1$$anonfun$apply$1.apply(AsyncCtrl.scala:77)
[error] 	at spinal.core.fiber.EngineContext$$anonfun$start$1$$anonfun$apply$1.apply(AsyncCtrl.scala:77)
[error] 	at spinal.core.Component.rework(Component.scala:364)
[error] 	at spinal.core.fiber.EngineContext$$anonfun$start$1.apply(AsyncCtrl.scala:77)
[error] 	at spinal.core.fiber.EngineContext$$anonfun$start$1.apply(AsyncCtrl.scala:73)
[error] 	at spinal.core.Component.walkComponents(Component.scala:129)
[error] 	at spinal.core.fiber.EngineContext.start(AsyncCtrl.scala:73)
[error] 	at spinal.core.fiber.Engine$.create(AsyncCtrl.scala:150)
[error] 	at spinal.core.internals.PhaseCreateComponent.impl(Phase.scala:2543)
[error] 	at spinal.core.internals.PhaseContext.doPhase(Phase.scala:183)
[error] 	at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2$$anonfun$apply$142.apply(Phase.scala:2918)
[error] 	at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2$$anonfun$apply$142.apply(Phase.scala:2916)
[error] 	at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error] 	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error] 	at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2.apply(Phase.scala:2916)
[error] 	at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2.apply(Phase.scala:2852)
[error] 	at spinal.core.ScopeProperty$.sandbox(ScopeProperty.scala:71)
[error] 	at spinal.core.internals.SpinalVerilogBoot$.singleShot(Phase.scala:2852)
[error] 	at spinal.core.internals.SpinalVerilogBoot$.apply(Phase.scala:2847)
[error] 	at spinal.core.Spinal$.apply(Spinal.scala:412)
[error] 	at spinal.core.SpinalConfig.generateVerilog(Spinal.scala:178)
[error] 	at spinal.core.sim.SpinalSimConfig.compileCloned(SimBootstraps.scala:927)
[error] 	at spinal.core.sim.SpinalSimConfig.compile(SimBootstraps.scala:897)
[error] 	at naxriscv.platform.tilelinkdemo.SocSim$.delayedEndpoint$naxriscv$platform$tilelinkdemo$SocSim$1(SocSim.scala:131)
[error] 	at naxriscv.platform.tilelinkdemo.SocSim$delayedInit$body.apply(SocSim.scala:52)
[error] 	at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
[error] 	at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
[error] 	at scala.App$$anonfun$main$1.apply(App.scala:76)
[error] 	at scala.App$$anonfun$main$1.apply(App.scala:76)
[error] 	at scala.collection.immutable.List.foreach(List.scala:392)
[error] 	at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
[error] 	at scala.App$class.main(App.scala:76)
[error] 	at naxriscv.platform.tilelinkdemo.SocSim$.main(SocSim.scala:52)
[error] 	at naxriscv.platform.tilelinkdemo.SocSim.main(SocSim.scala)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 159 s (02:39), completed Nov 6, 2023, 8:06:01 PM
sbt:NaxRiscv> 

[Dolu1990]

Hi,

Do i need to multiply with maschine hard id (mhartid) csrr x1, mhartid

If you want to print the stats of the current core, yes.

what is the maximum count of Nax that be possible to simulate ?

The only limit are the PLIC / CLINT / Scope memory mapping.
Currently you are hitting the scope one, if you rearange it's internal memory mapping you can make each CPU use less address space.

[SoCScholar]

If we want to do it in FPGA ( litex), Does the PLIC / CLINT / Scope memory mapping limit matter without rearranging it's internal memory mapping?

[Dolu1990]

Yes it does