From 1b788495ac62d6c11a684ccb87dff6b35e9beaaa Mon Sep 17 00:00:00 2001 From: Fredrik Noring Date: Sun, 13 Jan 2019 17:42:22 +0100 Subject: [PATCH] target/mips: Introduce the R5900 shift amount (SA) register [#4] Signed-off-by: Fredrik Noring --- target/mips/cpu.h | 1 + target/mips/translate.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 80a18d53acce..cc7ed0d187d9 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -182,6 +182,7 @@ struct TCState { /* Upper 64-bit multimedia registers (MMRs); the lower 64-bit are GPRs */ uint64_t mmr[32]; + uint32_t sar; /* Shift amount (SA) register */ }; typedef struct CPUMIPSState CPUMIPSState; diff --git a/target/mips/translate.c b/target/mips/translate.c index b71e5ee2ec01..ff9e3a26f663 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2468,6 +2468,7 @@ static TCGv_i64 msa_wr_d[64]; #if defined(TARGET_MIPS64) /* Upper 64-bit multimedia registers (MMRs); the lower 64-bit are GPRs */ static TCGv_i64 cpu_mmr[32]; +static TCGv_i32 cpu_sar; /* Shift amount (SA) register */ #else /* MXU registers */ static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; @@ -29935,6 +29936,10 @@ void mips_tcg_init(void) offsetof(CPUMIPSState, active_tc.mmr[i]), regnames[i]); + cpu_sar = tcg_global_mem_new_i32(cpu_env, + offsetof(CPUMIPSState, + active_tc.sar), + "sa"); #else for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { mxu_gpr[i] = tcg_global_mem_new(cpu_env,