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The algorithm uses temporaries t0--t3 to copy data from from flash to RAM. However, the RV32E removes registers x16--x31, which includes t3 / x28, therefore making this algorithm unavailable on RVE.
Proposals for a solution
We could pick another register in range x0--x16 in place of t3 to make the code compatible between RVI and RVE
We could #[cfg(riscve)] the algorithm to use another register on RV32E.
The text was updated successfully, but these errors were encountered:
I personally prefer using another register that fits all the specifications
hegza
changed the title
Assembly algorithm for RAM init incompatible with upcoming RVE extension (future proofing)riscv-rt: Assembly algorithm for RAM init incompatible with upcoming RVE extension (future proofing)
Feb 25, 2024
The RAM init function is incompatible with (as of yet, unratified) RV32E base ISA.
riscv/riscv-rt/src/asm.rs
Lines 147 to 158 in f5a2da9
The algorithm uses temporaries t0--t3 to copy data from from flash to RAM. However, the RV32E removes registers
x16
--x31
, which includest3
/x28
, therefore making this algorithm unavailable on RVE.Proposals for a solution
x0--x16
in place oft3
to make the code compatible between RVI and RVE#[cfg(riscve)]
the algorithm to use another register on RV32E.The text was updated successfully, but these errors were encountered: