From d3743601e0f5e87ee5f9d6754d27498f4964a926 Mon Sep 17 00:00:00 2001 From: Mudit Mishra Date: Thu, 15 Aug 2024 11:58:39 -0700 Subject: [PATCH 1/6] added pcie extended flag in AxiPcieCore --- python/axipcie/_AxiPcieCore.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/python/axipcie/_AxiPcieCore.py b/python/axipcie/_AxiPcieCore.py index 92bef23..22aedce 100644 --- a/python/axipcie/_AxiPcieCore.py +++ b/python/axipcie/_AxiPcieCore.py @@ -29,6 +29,7 @@ def __init__(self, useSpi = False, numDmaLanes = 1, boardType = None, + extended = False, sim = False, **kwargs): super().__init__(description=description, **kwargs) @@ -88,10 +89,11 @@ def __init__(self, )) # I2C access is slow. So using a AXI-Lite proxy to prevent holding up CPU during a BAR0 memory map transaction - self.add(axi.AxiLiteMasterProxy( - name = 'AxilBridge', - offset = 0x70000, - )) + if (extended): + self.add(axi.AxiLiteMasterProxy( + name = 'AxilBridge', + offset = 0x70000, + )) # Check for the SLAC GEN4 PGP Card if (boardType == 'SlacPgpCardG4'): From 691f6f9638e16085e840ec17f27704aaced53954 Mon Sep 17 00:00:00 2001 From: Mudit Mishra Date: Thu, 15 Aug 2024 13:09:23 -0700 Subject: [PATCH 2/6] added pcie extended flag in AxiPcieCore --- python/axipcie/_AxiPcieCore.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/axipcie/_AxiPcieCore.py b/python/axipcie/_AxiPcieCore.py index 22aedce..f12bfd9 100644 --- a/python/axipcie/_AxiPcieCore.py +++ b/python/axipcie/_AxiPcieCore.py @@ -89,7 +89,7 @@ def __init__(self, )) # I2C access is slow. So using a AXI-Lite proxy to prevent holding up CPU during a BAR0 memory map transaction - if (extended): + if not (extended): self.add(axi.AxiLiteMasterProxy( name = 'AxilBridge', offset = 0x70000, From d3d02520d51e182c8c9706bd4a3c31ae534a030f Mon Sep 17 00:00:00 2001 From: mmishra9 Date: Fri, 16 Aug 2024 12:07:15 -0700 Subject: [PATCH 3/6] fixed spaces --- python/axipcie/_AxiPcieCore.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/axipcie/_AxiPcieCore.py b/python/axipcie/_AxiPcieCore.py index f12bfd9..9275279 100644 --- a/python/axipcie/_AxiPcieCore.py +++ b/python/axipcie/_AxiPcieCore.py @@ -90,7 +90,7 @@ def __init__(self, # I2C access is slow. So using a AXI-Lite proxy to prevent holding up CPU during a BAR0 memory map transaction if not (extended): - self.add(axi.AxiLiteMasterProxy( + self.add(axi.AxiLiteMasterProxy( name = 'AxilBridge', offset = 0x70000, )) From f332d3cb9946651cbd02f43e995db7cc8886adb7 Mon Sep 17 00:00:00 2001 From: mmishra9 Date: Fri, 16 Aug 2024 12:14:09 -0700 Subject: [PATCH 4/6] fixed spaces --- python/axipcie/_AxiPcieCore.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/axipcie/_AxiPcieCore.py b/python/axipcie/_AxiPcieCore.py index 9275279..d5a1775 100644 --- a/python/axipcie/_AxiPcieCore.py +++ b/python/axipcie/_AxiPcieCore.py @@ -93,7 +93,7 @@ def __init__(self, self.add(axi.AxiLiteMasterProxy( name = 'AxilBridge', offset = 0x70000, - )) + )) # Check for the SLAC GEN4 PGP Card if (boardType == 'SlacPgpCardG4'): From 62b9d67b8984105cbb5a1f31c8d501850a3b05c1 Mon Sep 17 00:00:00 2001 From: Mudit Mishra Date: Mon, 19 Aug 2024 12:12:46 -0700 Subject: [PATCH 5/6] dumped rdLatency, updated gpuLatency --- .../gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd | 17 +++-------------- python/axipcie/_AxiGpuAsyncCore.py | 8 -------- 2 files changed, 3 insertions(+), 22 deletions(-) diff --git a/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd b/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd index 3f1ed85..26aa44b 100644 --- a/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd +++ b/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd @@ -103,8 +103,6 @@ architecture mapping of AxiPcieGpuAsyncControl is gpuLatencyEn : slv(MAX_BUFFERS_G-1 downto 0); wrLatency : Slv32Array(MAX_BUFFERS_G-1 downto 0); wrLatencyEn : slv(MAX_BUFFERS_G-1 downto 0); - rdLatency : Slv32Array(MAX_BUFFERS_G-1 downto 0); - rdLatencyEn : slv(MAX_BUFFERS_G-1 downto 0); readSlave : AxiLiteReadSlaveType; writeSlave : AxiLiteWriteSlaveType; dmaWrDescAck : AxiWriteDmaDescAckType; @@ -147,8 +145,6 @@ architecture mapping of AxiPcieGpuAsyncControl is gpuLatencyEn => (others => '0'), wrLatency => (others => (others => '0')), wrLatencyEn => (others => '0'), - rdLatency => (others => (others => '0')), - rdLatencyEn => (others => '0'), readSlave => AXI_LITE_READ_SLAVE_INIT_C, writeSlave => AXI_LITE_WRITE_SLAVE_INIT_C, dmaWrDescAck => AXI_WRITE_DMA_DESC_ACK_INIT_C, @@ -229,9 +225,6 @@ begin if r.wrLatencyEn(i) = '1' then v.wrLatency(i) := r.wrLatency(i) + 1; end if; - if r.rdLatencyEn(i) = '1' then - v.rdLatency(i) := r.rdLatency(i) + 1; - end if; end loop; -------------------------------------------------------------------------------------------- @@ -287,7 +280,6 @@ begin axiSlaveRegisterR(axilEp, toSlv(1280+i*16+0, 12), 0, r.totLatency(i)); -- 0x5x0 (x = 0,4,8,C....) axiSlaveRegisterR(axilEp, toSlv(1280+i*16+4, 12), 0, r.gpuLatency(i)); -- 0x5x4 (x = 0,4,8,C....) axiSlaveRegisterR(axilEp, toSlv(1280+i*16+8, 12), 0, r.wrLatency(i)); -- 0x5x8 (x = 0,4,8,C....) - axiSlaveRegisterR(axilEp, toSlv(1280+i*16+12, 12), 0, r.rdLatency(i)); -- 0x5xc (x = 0,4,8,C....) end loop; -- Closeout the transaction @@ -299,6 +291,9 @@ begin when IDLE_S => + if r.writeEnable = '0' then + v.gpuLatencyEn(conv_integer(r.nextWriteIdx)) := '0'; + end if; if dmaWrDescReq.valid = '1' then v.dmaWrDescAck.dropEn := not r.writeEnable; v.dmaWrDescAck.maxSize := r.remoteWriteSize(conv_integer(r.nextWriteIdx)); @@ -328,9 +323,6 @@ begin v.wrLatencyEn(conv_integer(r.nextWriteIdx)) := '1'; v.wrLatency(conv_integer(r.nextWriteIdx)) := (others => '0'); - v.rdLatencyEn(conv_integer(r.nextWriteIdx)) := '0'; - v.rdLatency(conv_integer(r.nextWriteIdx)) := (others => '0'); - if r.nextWriteIdx = r.writeCount then v.nextWriteIdx := (others => '0'); else @@ -369,8 +361,6 @@ begin if r.readEnable = '1' and r.remoteReadEn(conv_integer(r.nextReadIdx)) = '1' then v.remoteReadEn(conv_integer(r.nextReadIdx)) := '0'; - v.rdLatencyEn(conv_integer(r.nextReadIdx)) := '1'; - v.gpuLatencyEn(conv_integer(r.nextReadIdx)) := '0'; if r.nextReadIdx = r.readCount then v.nextReadIdx := (others => '0'); @@ -399,7 +389,6 @@ begin if dmaRdDescRet.valid = '1' then v.dmaRdDescRetAck := '1'; - v.rdLatencyEn(conv_integer(dmaRdDescRet.buffId(3 downto 0))) := '0'; v.totLatencyEn(conv_integer(dmaRdDescRet.buffId(3 downto 0))) := '0'; if dmaRdDescRet.result /= "000" then diff --git a/python/axipcie/_AxiGpuAsyncCore.py b/python/axipcie/_AxiGpuAsyncCore.py index 66172db..42b89c4 100644 --- a/python/axipcie/_AxiGpuAsyncCore.py +++ b/python/axipcie/_AxiGpuAsyncCore.py @@ -254,14 +254,6 @@ def __init__(self, pollInterval = 1, )) - self.add(pr.RemoteVariable( - name = f'RdLatency[{i}]', - offset = 0x50C + i*16, - bitSize = 32, - disp = '{}', - mode = 'RO', - pollInterval = 1, - )) def countReset(self): self.CountReset() From ddd22c25e82c027f07f552258a0ac95a8fb4a528 Mon Sep 17 00:00:00 2001 From: Mudit Mishra Date: Wed, 21 Aug 2024 08:35:59 -0700 Subject: [PATCH 6/6] updated gpuLatency counter --- protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd b/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd index 26aa44b..943be18 100644 --- a/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd +++ b/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd @@ -291,7 +291,7 @@ begin when IDLE_S => - if r.writeEnable = '0' then + if r.remoteWriteEn(conv_integer(r.nextWriteIdx)) = '0' then v.gpuLatencyEn(conv_integer(r.nextWriteIdx)) := '0'; end if; if dmaWrDescReq.valid = '1' then