From 7d9cbb41d1a27af41c515646f3ea1cc46f7c8506 Mon Sep 17 00:00:00 2001 From: Ryan Herbst Date: Thu, 25 Apr 2024 16:50:36 -0700 Subject: [PATCH 1/2] Add error capture --- .../gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd | 41 +++++++++---- python/axipcie/_AxiGpuAsyncCore.py | 60 +++++++++++++++++-- 2 files changed, 87 insertions(+), 14 deletions(-) diff --git a/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd b/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd index 7471211d..d670f017 100644 --- a/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd +++ b/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd @@ -74,7 +74,9 @@ architecture mapping of AxiPcieGpuAsyncControl is rxFrameCnt : slv(31 downto 0); txFrameCnt : slv(31 downto 0); axiWriteErrorCnt : slv(31 downto 0); + axiWriteErrorVal : slv(2 downto 0); axiReadErrorCnt : slv(31 downto 0); + axiReadErrorVal : slv(2 downto 0); cntRst : sl; awcache : slv(3 downto 0); arcache : slv(3 downto 0); @@ -84,10 +86,12 @@ architecture mapping of AxiPcieGpuAsyncControl is readCount : slv(3 downto 0); nextWriteIdx : slv(3 downto 0); nextReadIdx : slv(3 downto 0); - remoteWriteAddr : Slv32Array(MAX_BUFFERS_G-1 downto 0); + remoteWriteAddrL : Slv32Array(MAX_BUFFERS_G-1 downto 0); + remoteWriteAddrH : Slv32Array(MAX_BUFFERS_G-1 downto 0); remoteWriteSize : Slv32Array(MAX_BUFFERS_G-1 downto 0); remoteWriteEn : slv(MAX_BUFFERS_G-1 downto 0); - remoteReadAddr : Slv32Array(MAX_BUFFERS_G-1 downto 0); + remoteReadAddrL : Slv32Array(MAX_BUFFERS_G-1 downto 0); + remoteReadAddrH : Slv32Array(MAX_BUFFERS_G-1 downto 0); remoteReadSize : Slv32Array(MAX_BUFFERS_G-1 downto 0); remoteReadEn : slv(MAX_BUFFERS_G-1 downto 0); totLatency : Slv32Array(MAX_BUFFERS_G-1 downto 0); @@ -112,7 +116,9 @@ architecture mapping of AxiPcieGpuAsyncControl is rxFrameCnt => (others => '0'), txFrameCnt => (others => '0'), axiWriteErrorCnt => (others => '0'), + axiWriteErrorVal => (others => '0'), axiReadErrorCnt => (others => '0'), + axiReadErrorVal => (others => '0'), cntRst => '0', awcache => (others => '0'), arcache => (others => '0'), @@ -122,10 +128,12 @@ architecture mapping of AxiPcieGpuAsyncControl is readCount => (others => '0'), nextWriteIdx => (others => '0'), nextReadIdx => (others => '0'), - remoteWriteAddr => (others => (others => '0')), + remoteWriteAddrL => (others => (others => '0')), + remoteWriteAddrH => (others => (others => '0')), remoteWriteSize => (others => (others => '0')), remoteWriteEn => (others => '0'), - remoteReadAddr => (others => (others => '0')), + remoteReadAddrL => (others => (others => '0')), + remoteReadAddrH => (others => (others => '0')), remoteReadSize => (others => (others => '0')), remoteReadEn => (others => '0'), totLatency => (others => (others => '0')), @@ -199,7 +207,9 @@ begin v.rxFrameCnt := (others => '0'); v.txFrameCnt := (others => '0'); v.axiWriteErrorCnt := (others => '0'); + v.axiWriteErrorVal := (others => '0'); v.axiReadErrorCnt := (others => '0'); + v.axiReadErrorVal := (others => '0'); end if; -- Latency Counters @@ -239,14 +249,20 @@ begin axiSlaveRegisterR(axilEp, x"01C", 0, r.axiReadErrorCnt); axiSlaveRegister (axilEp, x"020", 0, v.cntRst); + axiSlaveRegisterR(axilEp, x"024", 0, r.axiWriteErrorVal); + axiSlaveRegisterR(axilEp, x"028", 0, r.axiReadErrorVal); + + for i in 0 to MAX_BUFFERS_G-1 loop - axiSlaveRegister (axilEp, toSlv(256+i*16+0, 12), 0, v.remoteWriteAddr(i)); -- 0x1x0 (x = 0,1,2,3....) - axiSlaveRegister (axilEp, toSlv(256+i*16+8, 12), 0, v.remoteWriteSize(i)); -- 0x1x8 (x = 0,1,2,3....) + axiSlaveRegister (axilEp, toSlv(256+i*16+0, 12), 0, v.remoteWriteAddrL(i)); -- 0x1x0 (x = 0,1,2,3....) + axiSlaveRegister (axilEp, toSlv(256+i*16+4, 12), 0, v.remoteWriteAddrH(i)); -- 0x1x4 (x = 0,1,2,3....) + axiSlaveRegister (axilEp, toSlv(256+i*16+8, 12), 0, v.remoteWriteSize(i)); -- 0x1x8 (x = 0,1,2,3....) end loop; for i in 0 to MAX_BUFFERS_G-1 loop - axiSlaveRegister (axilEp, toSlv(512+i*16+0, 12), 0, v.remoteReadAddr(i)); -- 0x2x0 (x = 0,1,2,3....) + axiSlaveRegister (axilEp, toSlv(512+i*16+0, 12), 0, v.remoteReadAddrL(i)); -- 0x2x0 (x = 0,1,2,3....) + axiSlaveRegister (axilEp, toSlv(512+i*16+0, 12), 0, v.remoteReadAddrH(i)); -- 0x2x4 (x = 0,1,2,3....) end loop; for i in 0 to MAX_BUFFERS_G-1 loop @@ -282,8 +298,10 @@ begin v.dmaWrDescAck.buffId(3 downto 0) := r.nextWriteIdx; - v.dmaWrDescAck.metaAddr(31 downto 0) := r.remoteWriteAddr(conv_integer(r.nextWriteIdx)); - v.dmaWrDescAck.address(31 downto 0) := r.remoteWriteAddr(conv_integer(r.nextWriteIdx)) + DMA_AXI_CONFIG_G.DATA_BYTES_C; + v.dmaWrDescAck.metaAddr(31 downto 0) := r.remoteWriteAddrL(conv_integer(r.nextWriteIdx)); + v.dmaWrDescAck.metaAddr(63 downto 32) := r.remoteWriteAddrH(conv_integer(r.nextWriteIdx)); + v.dmaWrDescAck.address(31 downto 0) := r.remoteWriteAddrL(conv_integer(r.nextWriteIdx)) + DMA_AXI_CONFIG_G.DATA_BYTES_C; + v.dmaWrDescAck.address(63 downto 32) := r.remoteWriteAddrH(conv_integer(r.nextWriteIdx)); if r.remoteWriteEn(conv_integer(r.nextWriteIdx)) = '1' or r.writeEnable = '0' then v.dmaWrDescAck.valid := '1'; @@ -324,6 +342,7 @@ begin if dmaWrDescRet.result /= "000" then v.axiWriteErrorCnt := r.axiWriteErrorCnt + 1; + v.axiWriteErrorVal := dmaWrDescRet.result; end if; v.rxFrameCnt := r.rxFrameCnt + 1; @@ -360,7 +379,8 @@ begin v.dmaRdDescReq.id := (others => '0'); v.dmaRdDescReq.dest := (others => '0'); - v.dmaRdDescReq.address(31 downto 0) := r.remoteReadAddr(conv_integer(r.nextReadIdx)); + v.dmaRdDescReq.address(31 downto 0) := r.remoteReadAddrL(conv_integer(r.nextReadIdx)); + v.dmaRdDescReq.address(63 downto 32) := r.remoteReadAddrH(conv_integer(r.nextReadIdx)); v.txState := MOVE_S; end if; @@ -375,6 +395,7 @@ begin if dmaRdDescRet.result /= "000" then v.axiReadErrorCnt := r.axiReadErrorCnt + 1; + v.axiReadErrorVal := dmaRdDescRet.result; end if; v.txFrameCnt := r.txFrameCnt + 1; diff --git a/python/axipcie/_AxiGpuAsyncCore.py b/python/axipcie/_AxiGpuAsyncCore.py index 1f31eb8e..673bb703 100644 --- a/python/axipcie/_AxiGpuAsyncCore.py +++ b/python/axipcie/_AxiGpuAsyncCore.py @@ -52,7 +52,7 @@ def __init__(self, )) self.add(pr.RemoteVariable( - name = 'BufferCount', + name = 'WriteCount', offset = 0x008, bitSize = 8, bitOffset = 0, @@ -62,7 +62,7 @@ def __init__(self, )) self.add(pr.RemoteVariable( - name = 'BufferEnable', + name = 'WriteEnable', offset = 0x008, bitSize = 1, bitOffset = 8, @@ -70,6 +70,25 @@ def __init__(self, pollInterval = 1, )) + self.add(pr.RemoteVariable( + name = 'ReadCount', + offset = 0x008, + bitSize = 8, + bitOffset = 16, + disp = '{}', + mode = 'RW', + pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'ReadEnable', + offset = 0x008, + bitSize = 1, + bitOffset = 24, + mode = 'RO', + pollInterval = 1, + )) + self.add(pr.RemoteVariable( name = 'RxFrameCnt', offset = 0x010, @@ -114,17 +133,42 @@ def __init__(self, function = pr.BaseCommand.touchOne )) + self.add(pr.RemoteVariable( + name = 'WriteAxiErrorVal', + offset = 0x024, + bitSize = 3, + disp = '{}', + mode = 'RO', + pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'ReadAxiErrorVal', + offset = 0x028, + bitSize = 3, + disp = '{}', + mode = 'RO', + pollInterval = 1, + )) for i in range(maxBuffers): self.add(pr.RemoteVariable( - name = f'RemoteWriteAddress[{i}]', + name = f'RemoteWriteAddressL[{i}]', offset = 0x100 + i*16, bitSize = 32, mode = 'RO', pollInterval = 1, )) + self.add(pr.RemoteVariable( + name = f'RemoteWriteAddressH[{i}]', + offset = 0x104 + i*16, + bitSize = 32, + mode = 'RO', + pollInterval = 1, + )) + self.add(pr.RemoteVariable( name = f'RemoteWriteSize[{i}]', offset = 0x108 + i*16, @@ -134,13 +178,21 @@ def __init__(self, )) self.add(pr.RemoteVariable( - name = f'RemoteReadAddress[{i}]', + name = f'RemoteReadAddressL[{i}]', offset = 0x200 + i*16, bitSize = 32, mode = 'RO', pollInterval = 1, )) + self.add(pr.RemoteVariable( + name = f'RemoteReadAddressH[{i}]', + offset = 0x204 + i*16, + bitSize = 32, + mode = 'RO', + pollInterval = 1, + )) + self.add(pr.RemoteVariable( name = f'RemoteReadSize[{i}]', offset = 0x400 + i*4, From 8d9ec217075c87555fb0dd223d7faed828250b5a Mon Sep 17 00:00:00 2001 From: Ryan Herbst Date: Thu, 25 Apr 2024 18:00:05 -0700 Subject: [PATCH 2/2] Fix read buffer address --- protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd | 2 +- python/axipcie/_AxiGpuAsyncCore.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd b/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd index d670f017..0e1779f1 100644 --- a/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd +++ b/protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd @@ -262,7 +262,7 @@ begin for i in 0 to MAX_BUFFERS_G-1 loop axiSlaveRegister (axilEp, toSlv(512+i*16+0, 12), 0, v.remoteReadAddrL(i)); -- 0x2x0 (x = 0,1,2,3....) - axiSlaveRegister (axilEp, toSlv(512+i*16+0, 12), 0, v.remoteReadAddrH(i)); -- 0x2x4 (x = 0,1,2,3....) + axiSlaveRegister (axilEp, toSlv(512+i*16+4, 12), 0, v.remoteReadAddrH(i)); -- 0x2x4 (x = 0,1,2,3....) end loop; for i in 0 to MAX_BUFFERS_G-1 loop diff --git a/python/axipcie/_AxiGpuAsyncCore.py b/python/axipcie/_AxiGpuAsyncCore.py index 673bb703..4434f66f 100644 --- a/python/axipcie/_AxiGpuAsyncCore.py +++ b/python/axipcie/_AxiGpuAsyncCore.py @@ -76,7 +76,7 @@ def __init__(self, bitSize = 8, bitOffset = 16, disp = '{}', - mode = 'RW', + mode = 'RO', pollInterval = 1, ))