From b543f716af4571d99d60b732e5e4a422cf12ac22 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 28 Jun 2022 15:30:49 -0700 Subject: [PATCH 1/3] adding MigDmaBuffer.vhd --- .../XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd | 290 ++++++++++++++++++ .../XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd | 290 ++++++++++++++++++ 2 files changed, 580 insertions(+) create mode 100644 hardware/XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd create mode 100644 hardware/XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd diff --git a/hardware/XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd b/hardware/XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd new file mode 100644 index 0000000..d91a0cb --- /dev/null +++ b/hardware/XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd @@ -0,0 +1,290 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: MIG DMA buffer +------------------------------------------------------------------------------- +-- This file is part of 'axi-pcie-core'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'axi-pcie-core', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; + +library axi_pcie_core; +use axi_pcie_core.MigPkg.all; + +entity MigDmaBuffer is + generic ( + TPD_G : time := 1 ns; + DMA_SIZE_G : positive range 1 to 8 := 8; + DMA_AXIS_CONFIG_G : AxiStreamConfigType; + AXIL_BASE_ADDR_G : slv(31 downto 0)); + port ( + -- AXI-Lite Interface (axilClk domain) + axilClk : in sl; + axilRst : in sl; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType; + -- Trigger Event streams (eventClk domain) + eventClk : in sl; + eventTrigMsgCtrl : out AxiStreamCtrlArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_CTRL_INIT_C); + -- AXI Stream Interface (axisClk domain) + axisClk : in sl; + axisRst : in sl; + sAxisMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + sAxisSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + mAxisMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + mAxisSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + -- DDR AXI MEM Interface + ddrClk : in slv(3 downto 0); + ddrRst : in slv(3 downto 0); + ddrReady : in slv(3 downto 0); + ddrWriteMasters : out AxiWriteMasterArray(3 downto 0); + ddrWriteSlaves : in AxiWriteSlaveArray(3 downto 0); + ddrReadMasters : out AxiReadMasterArray(3 downto 0); + ddrReadSlaves : in AxiReadSlaveArray(3 downto 0)); +end MigDmaBuffer; + +architecture mapping of MigDmaBuffer is + + constant AXI_BUFFER_WIDTH_C : positive := MEM_AXI_CONFIG_C.ADDR_WIDTH_C-1; -- 1 DDR DIMM split between 2 DMA lanes + constant AXI_BASE_ADDR_C : Slv64Array(1 downto 0) := ( + 0 => toSlv(0, 64), + 1 => toSlv(2**AXI_BUFFER_WIDTH_C, 64)); -- Units of bytes + + constant INT_DMA_AXIS_CONFIG_C : AxiStreamConfigType := ( + TSTRB_EN_C => false, + TDATA_BYTES_C => DMA_AXIS_CONFIG_G.TDATA_BYTES_C, + TDEST_BITS_C => 8, + TID_BITS_C => 3, + TKEEP_MODE_C => TKEEP_COUNT_C, -- AXI DMA V2 uses TKEEP_COUNT_C to help meet timing + TUSER_BITS_C => 4, + TUSER_MODE_C => TUSER_FIRST_LAST_C); + + constant DMA_AXI_CONFIG_C : AxiConfigType := ( + ADDR_WIDTH_C => 40, -- Match 40-bit address for axi_pcie_core.AxiPcieCrossbar + DATA_BYTES_C => INT_DMA_AXIS_CONFIG_C.TDATA_BYTES_C, -- Matches the AXIS stream + ID_BITS_C => MEM_AXI_CONFIG_C.ID_BITS_C, + LEN_BITS_C => MEM_AXI_CONFIG_C.LEN_BITS_C); + + constant INT_DMA_AXI_CONFIG_C : AxiConfigType := ( + ADDR_WIDTH_C => 40, -- Match 40-bit address for axi_pcie_core.AxiPcieCrossbar + DATA_BYTES_C => MEM_AXI_CONFIG_C.DATA_BYTES_C, -- Actual memory interface width + ID_BITS_C => MEM_AXI_CONFIG_C.ID_BITS_C, + LEN_BITS_C => MEM_AXI_CONFIG_C.LEN_BITS_C); + + constant AXIL_XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(DMA_SIZE_G-1 downto 0) := genAxiLiteConfig(DMA_SIZE_G, AXIL_BASE_ADDR_G, 12, 8); + + signal axilWriteMasters : AxiLiteWriteMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_LITE_WRITE_MASTER_INIT_C); + signal axilWriteSlaves : AxiLiteWriteSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); + signal axilReadMasters : AxiLiteReadMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_LITE_READ_MASTER_INIT_C); + signal axilReadSlaves : AxiLiteReadSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C); + + signal axiWriteMasters : AxiWriteMasterArray(7 downto 0) := (others => AXI_WRITE_MASTER_INIT_C); + signal axiWriteSlaves : AxiWriteSlaveArray(7 downto 0) := (others => AXI_WRITE_SLAVE_INIT_C); + signal axiReadMasters : AxiReadMasterArray(7 downto 0) := (others => AXI_READ_MASTER_INIT_C); + signal axiReadSlaves : AxiReadSlaveArray(7 downto 0) := (others => AXI_READ_SLAVE_INIT_C); + + signal unusedWriteMasters : AxiWriteMasterArray(7 downto 0) := (others => AXI_WRITE_MASTER_INIT_C); + signal unusedWriteSlaves : AxiWriteSlaveArray(7 downto 0) := (others => AXI_WRITE_SLAVE_INIT_C); + signal unusedReadMasters : AxiReadMasterArray(7 downto 0) := (others => AXI_READ_MASTER_INIT_C); + signal unusedReadSlaves : AxiReadSlaveArray(7 downto 0) := (others => AXI_READ_SLAVE_INIT_C); + + signal sAxisCtrl : AxiStreamCtrlArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_CTRL_INIT_C); + + signal rxMasters : AxiStreamMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal rxSlaves : AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + signal txMasters : AxiStreamMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal txSlaves : AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + + signal ddrClock : slv(7 downto 0); + signal ddrReset : slv(7 downto 0); + signal ddrRdy : slv(7 downto 0); + signal axisReset : slv(7 downto 0); + +begin + + ddrClock <= ddrClk(3) & ddrClk(3) & ddrClk(2) & ddrClk(2) & ddrClk(1) & ddrClk(1) & ddrClk(0) & ddrClk(0); + ddrReset <= ddrRst(3) & ddrRst(3) & ddrRst(2) & ddrRst(2) & ddrRst(1) & ddrRst(1) & ddrRst(0) & ddrRst(0); + ddrRdy <= ddrReady(3) & ddrReady(3) & ddrReady(2) & ddrReady(2) & ddrReady(1) & ddrReady(1) & ddrReady(0) & ddrReady(0); + + -------------------- + -- AXI-Lite Crossbar + -------------------- + U_XBAR : entity surf.AxiLiteCrossbar + generic map ( + TPD_G => TPD_G, + NUM_SLAVE_SLOTS_G => 1, + NUM_MASTER_SLOTS_G => DMA_SIZE_G, + MASTERS_CONFIG_G => AXIL_XBAR_CONFIG_C) + port map ( + axiClk => axilClk, + axiClkRst => axilRst, + sAxiWriteMasters(0) => axilWriteMaster, + sAxiWriteSlaves(0) => axilWriteSlave, + sAxiReadMasters(0) => axilReadMaster, + sAxiReadSlaves(0) => axilReadSlave, + mAxiWriteMasters => axilWriteMasters, + mAxiWriteSlaves => axilWriteSlaves, + mAxiReadMasters => axilReadMasters, + mAxiReadSlaves => axilReadSlaves); + + GEN_FIFO : for i in DMA_SIZE_G-1 downto 0 generate + + -- Help with timing + U_AxisRst : entity surf.RstPipeline + generic map ( + TPD_G => TPD_G, + INV_RST_G => false) + port map ( + clk => axisClk, + rstIn => axisRst, + rstOut => axisReset(i)); + + -------------------------- + -- Inbound AXI Stream FIFO + -------------------------- + U_IbFifo : entity surf.AxiStreamFifoV2 + generic map ( + -- General Configurations + TPD_G => TPD_G, + SLAVE_READY_EN_G => true, + VALID_THOLD_G => 1, + -- FIFO configurations + MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => false, + FIFO_ADDR_WIDTH_G => 9, + -- AXI Stream Port Configurations + SLAVE_AXI_CONFIG_G => DMA_AXIS_CONFIG_G, + MASTER_AXI_CONFIG_G => INT_DMA_AXIS_CONFIG_C) + port map ( + -- Slave Port + sAxisClk => axisClk, + sAxisRst => axisReset(i), + sAxisMaster => sAxisMasters(i), + sAxisSlave => sAxisSlaves(i), + -- Master Port + mAxisClk => ddrClock(i), + mAxisRst => ddrReset(i), + mAxisMaster => rxMasters(i), + mAxisSlave => rxSlaves(i)); + + U_AxiFifo : entity surf.AxiStreamDmaV2Fifo + generic map ( + TPD_G => TPD_G, + -- FIFO Configuration + BUFF_FRAME_WIDTH_G => AXI_BUFFER_WIDTH_C-12, -- Optimized to fix into 1 URAM (12-bit address) for free list + AXI_BUFFER_WIDTH_G => AXI_BUFFER_WIDTH_C, + SYNTH_MODE_G => "xpm", + MEMORY_TYPE_G => "ultra", + -- AXI Stream Configurations + AXIS_CONFIG_G => INT_DMA_AXIS_CONFIG_C, + -- AXI4 Configurations + AXI_BASE_ADDR_G => AXI_BASE_ADDR_C(i mod 2), + AXI_CONFIG_G => DMA_AXI_CONFIG_C) + port map ( + -- AXI4 Interface (axiClk domain) + axiClk => ddrClock(i), + axiRst => ddrReset(i), + axiReady => ddrRdy(i), + axiReadMaster => axiReadMasters(i), + axiReadSlave => axiReadSlaves(i), + axiWriteMaster => axiWriteMasters(i), + axiWriteSlave => axiWriteSlaves(i), + -- AXI Stream Interface (axiClk domain) + sAxisMaster => rxMasters(i), + sAxisSlave => rxSlaves(i), + sAxisCtrl => sAxisCtrl(i), + mAxisMaster => txMasters(i), + mAxisSlave => txSlaves(i), + -- Optional: AXI-Lite Interface (axilClk domain) + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMasters(i), + axilReadSlave => axilReadSlaves(i), + axilWriteMaster => axilWriteMasters(i), + axilWriteSlave => axilWriteSlaves(i)); + + U_pause : entity surf.Synchronizer + generic map ( + TPD_G => TPD_G) + port map ( + clk => eventClk, + dataIn => sAxisCtrl(i).pause, + dataOut => eventTrigMsgCtrl(i).pause); + + U_ObFifo : entity surf.AxiStreamFifoV2 + generic map ( + -- General Configurations + TPD_G => TPD_G, + SLAVE_READY_EN_G => true, + VALID_THOLD_G => 1, + -- FIFO configurations + MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => false, + FIFO_ADDR_WIDTH_G => 9, + -- AXI Stream Port Configurations + SLAVE_AXI_CONFIG_G => INT_DMA_AXIS_CONFIG_C, + MASTER_AXI_CONFIG_G => DMA_AXIS_CONFIG_G) + port map ( + -- Slave Port + sAxisClk => ddrClock(i), + sAxisRst => ddrReset(i), + sAxisMaster => txMasters(i), + sAxisSlave => txSlaves(i), + -- Master Port + mAxisClk => axisClk, + mAxisRst => axisReset(i), + mAxisMaster => mAxisMasters(i), + mAxisSlave => mAxisSlaves(i)); + + end generate; + + GEN_XBAR : for i in 3 downto 0 generate + -- Reuse the AxiPcieCrossbar for the MIGT DMA Buffer + U_XBAR : entity axi_pcie_core.AxiPcieCrossbar + generic map ( + TPD_G => TPD_G, + AXI_DMA_CONFIG_G => DMA_AXI_CONFIG_C, + AXI_PCIE_CONFIG_G => INT_DMA_AXI_CONFIG_C, + DMA_SIZE_G => 2) + port map ( + axiClk => ddrClk(i), + axiRst => ddrRst(i), + -- Slave Write Masters + sAxiWriteMasters(3) => unusedWriteMasters(i+4), -- General Purpose AXI path + sAxiWriteMasters(2 downto 1) => axiWriteMasters(2*i+1 downto 2*i), + sAxiWriteMasters(0) => unusedWriteMasters(i+0), -- PIP path + -- Slave Write Slaves + sAxiWriteSlaves(3) => unusedWriteSlaves(i+4), -- General Purpose AXI path + sAxiWriteSlaves(2 downto 1) => axiWriteSlaves(2*i+1 downto 2*i), + sAxiWriteSlaves(0) => unusedWriteSlaves(i+0), -- PIP path + -- Slave Read Masters + sAxiReadMasters(3) => unusedReadMasters(i+4), -- General Purpose AXI path + sAxiReadMasters(2 downto 1) => axiReadMasters(2*i+1 downto 2*i), + sAxiReadMasters(0) => unusedReadMasters(i+0), -- PIP path + -- Slave Read Slaves + sAxiReadSlaves(3) => unusedReadSlaves(i+4), -- General Purpose AXI path + sAxiReadSlaves(2 downto 1) => axiReadSlaves(2*i+1 downto 2*i), + sAxiReadSlaves(0) => unusedReadSlaves(i+0), -- PIP path + -- Master + mAxiWriteMaster => ddrWriteMasters(i), + mAxiWriteSlave => ddrWriteSlaves(i), + mAxiReadMaster => ddrReadMasters(i), + mAxiReadSlave => ddrReadSlaves(i)); + end generate; + +end mapping; diff --git a/hardware/XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd b/hardware/XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd new file mode 100644 index 0000000..c65a322 --- /dev/null +++ b/hardware/XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd @@ -0,0 +1,290 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: MIG DMA buffer +------------------------------------------------------------------------------- +-- This file is part of 'axi-pcie-core'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'axi-pcie-core', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; + +library axi_pcie_core; +use axi_pcie_core.MigPkg.all; + +entity MigDmaBuffer is + generic ( + TPD_G : time := 1 ns; + DMA_SIZE_G : positive range 1 to 8 := 8; + DMA_AXIS_CONFIG_G : AxiStreamConfigType; + AXIL_BASE_ADDR_G : slv(31 downto 0)); + port ( + -- AXI-Lite Interface (axilClk domain) + axilClk : in sl; + axilRst : in sl; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType; + -- Trigger Event streams (eventClk domain) + eventClk : in sl; + eventTrigMsgCtrl : out AxiStreamCtrlArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_CTRL_INIT_C); + -- AXI Stream Interface (axisClk domain) + axisClk : in sl; + axisRst : in sl; + sAxisMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + sAxisSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + mAxisMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + mAxisSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + -- DDR AXI MEM Interface + ddrClk : in slv(3 downto 0); + ddrRst : in slv(3 downto 0); + ddrReady : in slv(3 downto 0); + ddrWriteMasters : out AxiWriteMasterArray(3 downto 0); + ddrWriteSlaves : in AxiWriteSlaveArray(3 downto 0); + ddrReadMasters : out AxiReadMasterArray(3 downto 0); + ddrReadSlaves : in AxiReadSlaveArray(3 downto 0)); +end MigDmaBuffer; + +architecture mapping of MigDmaBuffer is + + constant AXI_BUFFER_WIDTH_C : positive := MEM_AXI_CONFIG_C.ADDR_WIDTH_C-1; -- 1 DDR DIMM split between 2 DMA lanes + constant AXI_BASE_ADDR_C : Slv64Array(1 downto 0) := ( + 0 => toSlv(0, 64), + 1 => toSlv(2**AXI_BUFFER_WIDTH_C, 64)); -- Units of bytes + + constant INT_DMA_AXIS_CONFIG_C : AxiStreamConfigType := ( + TSTRB_EN_C => false, + TDATA_BYTES_C => DMA_AXIS_CONFIG_G.TDATA_BYTES_C, + TDEST_BITS_C => 8, + TID_BITS_C => 3, + TKEEP_MODE_C => TKEEP_COUNT_C, -- AXI DMA V2 uses TKEEP_COUNT_C to help meet timing + TUSER_BITS_C => 4, + TUSER_MODE_C => TUSER_FIRST_LAST_C); + + constant DMA_AXI_CONFIG_C : AxiConfigType := ( + ADDR_WIDTH_C => 40, -- Match 40-bit address for axi_pcie_core.AxiPcieCrossbar + DATA_BYTES_C => INT_DMA_AXIS_CONFIG_C.TDATA_BYTES_C, -- Matches the AXIS stream + ID_BITS_C => MEM_AXI_CONFIG_C.ID_BITS_C, + LEN_BITS_C => MEM_AXI_CONFIG_C.LEN_BITS_C); + + constant INT_DMA_AXI_CONFIG_C : AxiConfigType := ( + ADDR_WIDTH_C => 40, -- Match 40-bit address for axi_pcie_core.AxiPcieCrossbar + DATA_BYTES_C => MEM_AXI_CONFIG_C.DATA_BYTES_C, -- Actual memory interface width + ID_BITS_C => MEM_AXI_CONFIG_C.ID_BITS_C, + LEN_BITS_C => MEM_AXI_CONFIG_C.LEN_BITS_C); + + constant AXIL_XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(DMA_SIZE_G-1 downto 0) := genAxiLiteConfig(DMA_SIZE_G, AXIL_BASE_ADDR_G, 12, 8); + + signal axilWriteMasters : AxiLiteWriteMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_LITE_WRITE_MASTER_INIT_C); + signal axilWriteSlaves : AxiLiteWriteSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); + signal axilReadMasters : AxiLiteReadMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_LITE_READ_MASTER_INIT_C); + signal axilReadSlaves : AxiLiteReadSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C); + + signal axiWriteMasters : AxiWriteMasterArray(7 downto 0) := (others => AXI_WRITE_MASTER_INIT_C); + signal axiWriteSlaves : AxiWriteSlaveArray(7 downto 0) := (others => AXI_WRITE_SLAVE_INIT_C); + signal axiReadMasters : AxiReadMasterArray(7 downto 0) := (others => AXI_READ_MASTER_INIT_C); + signal axiReadSlaves : AxiReadSlaveArray(7 downto 0) := (others => AXI_READ_SLAVE_INIT_C); + + signal unusedWriteMasters : AxiWriteMasterArray(7 downto 0) := (others => AXI_WRITE_MASTER_INIT_C); + signal unusedWriteSlaves : AxiWriteSlaveArray(7 downto 0) := (others => AXI_WRITE_SLAVE_INIT_C); + signal unusedReadMasters : AxiReadMasterArray(7 downto 0) := (others => AXI_READ_MASTER_INIT_C); + signal unusedReadSlaves : AxiReadSlaveArray(7 downto 0) := (others => AXI_READ_SLAVE_INIT_C); + + signal sAxisCtrl : AxiStreamCtrlArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_CTRL_INIT_C); + + signal rxMasters : AxiStreamMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal rxSlaves : AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + signal txMasters : AxiStreamMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal txSlaves : AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + + signal ddrClock : slv(7 downto 0); + signal ddrReset : slv(7 downto 0); + signal ddrRdy : slv(7 downto 0); + signal axisReset : slv(7 downto 0); + +begin + + ddrClock <= ddrClk(3) & ddrClk(3) & ddrClk(2) & ddrClk(2) & ddrClk(1) & ddrClk(1) & ddrClk(0) & ddrClk(0); + ddrReset <= ddrRst(3) & ddrRst(3) & ddrRst(2) & ddrRst(2) & ddrRst(1) & ddrRst(1) & ddrRst(0) & ddrRst(0); + ddrRdy <= ddrReady(3) & ddrReady(3) & ddrReady(2) & ddrReady(2) & ddrReady(1) & ddrReady(1) & ddrReady(0) & ddrReady(0); + + -------------------- + -- AXI-Lite Crossbar + -------------------- + U_XBAR : entity surf.AxiLiteCrossbar + generic map ( + TPD_G => TPD_G, + NUM_SLAVE_SLOTS_G => 1, + NUM_MASTER_SLOTS_G => DMA_SIZE_G, + MASTERS_CONFIG_G => AXIL_XBAR_CONFIG_C) + port map ( + axiClk => axilClk, + axiClkRst => axilRst, + sAxiWriteMasters(0) => axilWriteMaster, + sAxiWriteSlaves(0) => axilWriteSlave, + sAxiReadMasters(0) => axilReadMaster, + sAxiReadSlaves(0) => axilReadSlave, + mAxiWriteMasters => axilWriteMasters, + mAxiWriteSlaves => axilWriteSlaves, + mAxiReadMasters => axilReadMasters, + mAxiReadSlaves => axilReadSlaves); + + GEN_FIFO : for i in DMA_SIZE_G-1 downto 0 generate + + -- Help with timing + U_AxisRst : entity surf.RstPipeline + generic map ( + TPD_G => TPD_G, + INV_RST_G => false) + port map ( + clk => axisClk, + rstIn => axisRst, + rstOut => axisReset(i)); + + -------------------------- + -- Inbound AXI Stream FIFO + -------------------------- + U_IbFifo : entity surf.AxiStreamFifoV2 + generic map ( + -- General Configurations + TPD_G => TPD_G, + SLAVE_READY_EN_G => true, + VALID_THOLD_G => 1, + -- FIFO configurations + MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => false, + FIFO_ADDR_WIDTH_G => 9, + -- AXI Stream Port Configurations + SLAVE_AXI_CONFIG_G => DMA_AXIS_CONFIG_G, + MASTER_AXI_CONFIG_G => INT_DMA_AXIS_CONFIG_C) + port map ( + -- Slave Port + sAxisClk => axisClk, + sAxisRst => axisReset(i), + sAxisMaster => sAxisMasters(i), + sAxisSlave => sAxisSlaves(i), + -- Master Port + mAxisClk => ddrClock(i), + mAxisRst => ddrReset(i), + mAxisMaster => rxMasters(i), + mAxisSlave => rxSlaves(i)); + + U_AxiFifo : entity surf.AxiStreamDmaV2Fifo + generic map ( + TPD_G => TPD_G, + -- FIFO Configuration + BUFF_FRAME_WIDTH_G => AXI_BUFFER_WIDTH_C-10, -- Optimized to fix into 1 BRAM (10-bit address) for free list + AXI_BUFFER_WIDTH_G => AXI_BUFFER_WIDTH_C, + SYNTH_MODE_G => "xpm", + MEMORY_TYPE_G => "block", + -- AXI Stream Configurations + AXIS_CONFIG_G => INT_DMA_AXIS_CONFIG_C, + -- AXI4 Configurations + AXI_BASE_ADDR_G => AXI_BASE_ADDR_C(i mod 2), + AXI_CONFIG_G => DMA_AXI_CONFIG_C) + port map ( + -- AXI4 Interface (axiClk domain) + axiClk => ddrClock(i), + axiRst => ddrReset(i), + axiReady => ddrRdy(i), + axiReadMaster => axiReadMasters(i), + axiReadSlave => axiReadSlaves(i), + axiWriteMaster => axiWriteMasters(i), + axiWriteSlave => axiWriteSlaves(i), + -- AXI Stream Interface (axiClk domain) + sAxisMaster => rxMasters(i), + sAxisSlave => rxSlaves(i), + sAxisCtrl => sAxisCtrl(i), + mAxisMaster => txMasters(i), + mAxisSlave => txSlaves(i), + -- Optional: AXI-Lite Interface (axilClk domain) + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMasters(i), + axilReadSlave => axilReadSlaves(i), + axilWriteMaster => axilWriteMasters(i), + axilWriteSlave => axilWriteSlaves(i)); + + U_pause : entity surf.Synchronizer + generic map ( + TPD_G => TPD_G) + port map ( + clk => eventClk, + dataIn => sAxisCtrl(i).pause, + dataOut => eventTrigMsgCtrl(i).pause); + + U_ObFifo : entity surf.AxiStreamFifoV2 + generic map ( + -- General Configurations + TPD_G => TPD_G, + SLAVE_READY_EN_G => true, + VALID_THOLD_G => 1, + -- FIFO configurations + MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => false, + FIFO_ADDR_WIDTH_G => 9, + -- AXI Stream Port Configurations + SLAVE_AXI_CONFIG_G => INT_DMA_AXIS_CONFIG_C, + MASTER_AXI_CONFIG_G => DMA_AXIS_CONFIG_G) + port map ( + -- Slave Port + sAxisClk => ddrClock(i), + sAxisRst => ddrReset(i), + sAxisMaster => txMasters(i), + sAxisSlave => txSlaves(i), + -- Master Port + mAxisClk => axisClk, + mAxisRst => axisReset(i), + mAxisMaster => mAxisMasters(i), + mAxisSlave => mAxisSlaves(i)); + + end generate; + + GEN_XBAR : for i in 3 downto 0 generate + -- Reuse the AxiPcieCrossbar for the MIG DMA Buffer + U_XBAR : entity axi_pcie_core.AxiPcieCrossbar + generic map ( + TPD_G => TPD_G, + AXI_DMA_CONFIG_G => DMA_AXI_CONFIG_C, + AXI_PCIE_CONFIG_G => INT_DMA_AXI_CONFIG_C, + DMA_SIZE_G => 2) + port map ( + axiClk => ddrClk(i), + axiRst => ddrRst(i), + -- Slave Write Masters + sAxiWriteMasters(3) => unusedWriteMasters(i+4), -- General Purpose AXI path + sAxiWriteMasters(2 downto 1) => axiWriteMasters(2*i+1 downto 2*i), + sAxiWriteMasters(0) => unusedWriteMasters(i+0), -- PIP path + -- Slave Write Slaves + sAxiWriteSlaves(3) => unusedWriteSlaves(i+4), -- General Purpose AXI path + sAxiWriteSlaves(2 downto 1) => axiWriteSlaves(2*i+1 downto 2*i), + sAxiWriteSlaves(0) => unusedWriteSlaves(i+0), -- PIP path + -- Slave Read Masters + sAxiReadMasters(3) => unusedReadMasters(i+4), -- General Purpose AXI path + sAxiReadMasters(2 downto 1) => axiReadMasters(2*i+1 downto 2*i), + sAxiReadMasters(0) => unusedReadMasters(i+0), -- PIP path + -- Slave Read Slaves + sAxiReadSlaves(3) => unusedReadSlaves(i+4), -- General Purpose AXI path + sAxiReadSlaves(2 downto 1) => axiReadSlaves(2*i+1 downto 2*i), + sAxiReadSlaves(0) => unusedReadSlaves(i+0), -- PIP path + -- Master + mAxiWriteMaster => ddrWriteMasters(i), + mAxiWriteSlave => ddrWriteSlaves(i), + mAxiReadMaster => ddrReadMasters(i), + mAxiReadSlave => ddrReadSlaves(i)); + end generate; + +end mapping; From 5ef6601bcefaf415f6cb3df6604195d2104592db Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 28 Jun 2022 19:12:25 -0700 Subject: [PATCH 2/3] updates for MigDmaBuffer --- .../XilinxAlveoU200/ddr/ip/MigClkConvt.xci | 160 ++++++++++++ .../ddr/ip/axi_infrastructure_v1_1_0.vh | 138 +++++++++++ .../ddr/rtl/MigClkConvtWrapper.vhd | 230 ++++++++++++++++++ .../XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd | 173 ++++++------- hardware/XilinxAlveoU200/ddr/ruckus.tcl | 3 + .../ddr/xdc/XilinxAlveoU200MigTiming.xdc | 24 ++ .../XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd | 175 ++++++------- .../ddr/xdc/XilinxKcu1500MigTiming.xdc | 24 ++ 8 files changed, 734 insertions(+), 193 deletions(-) create mode 100644 hardware/XilinxAlveoU200/ddr/ip/MigClkConvt.xci create mode 100644 hardware/XilinxAlveoU200/ddr/ip/axi_infrastructure_v1_1_0.vh create mode 100644 hardware/XilinxAlveoU200/ddr/rtl/MigClkConvtWrapper.vhd diff --git a/hardware/XilinxAlveoU200/ddr/ip/MigClkConvt.xci b/hardware/XilinxAlveoU200/ddr/ip/MigClkConvt.xci new file mode 100644 index 0000000..0413ee2 --- /dev/null +++ b/hardware/XilinxAlveoU200/ddr/ip/MigClkConvt.xci @@ -0,0 +1,160 @@ + + + xilinx.com + xci + unknown + 1.0 + + + MigClkConvt + + + + + + 10000000 + 0 + 0.000 + 0 + ACTIVE_LOW + 64 + 0 + 0 + 0 + + 512 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + + + + 10000000 + 0 + 0.000 + 0 + ACTIVE_LOW + 64 + 0 + 0 + 0 + + 512 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 64 + 1 + 1 + 1 + 512 + 4 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + virtexuplus + 2 + 4 + 1 + 1 + 1:2 + 64 + 0 + 0 + 0 + MigClkConvt + 512 + 4 + AXI4 + READ_WRITE + 0 + 4 + 0 + virtexuplus + xilinx.com:au250:part0:1.0 + + xcu250 + figd2104 + VERILOG + + MIXED + -2L + E + TRUE + TRUE + IP_Flow + 17 + TRUE + . + + . + 2018.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/XilinxAlveoU200/ddr/ip/axi_infrastructure_v1_1_0.vh b/hardware/XilinxAlveoU200/ddr/ip/axi_infrastructure_v1_1_0.vh new file mode 100644 index 0000000..d3d4a0e --- /dev/null +++ b/hardware/XilinxAlveoU200/ddr/ip/axi_infrastructure_v1_1_0.vh @@ -0,0 +1,138 @@ +// (c) Copyright 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Generic Functions used by AXI Infrastructure Modules +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// Global Parameters: +// +// Functions: +// +// Tasks: +//-------------------------------------------------------------------------- +/////////////////////////////////////////////////////////////////////////////// +// BEGIN Global Parameters +/////////////////////////////////////////////////////////////////////////////// +localparam G_AXI_AWADDR_INDEX = 0; +localparam G_AXI_AWADDR_WIDTH = C_AXI_ADDR_WIDTH; +localparam G_AXI_AWPROT_INDEX = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH; +localparam G_AXI_AWPROT_WIDTH = 3; +localparam G_AXI_AWSIZE_INDEX = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH; +localparam G_AXI_AWSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3; +localparam G_AXI_AWBURST_INDEX = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH; +localparam G_AXI_AWBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2; +localparam G_AXI_AWCACHE_INDEX = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH; +localparam G_AXI_AWCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_AWLEN_INDEX = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH; +localparam G_AXI_AWLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8; +localparam G_AXI_AWLOCK_INDEX = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH; +localparam G_AXI_AWLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1; +localparam G_AXI_AWID_INDEX = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH; +localparam G_AXI_AWID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_AWQOS_INDEX = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH; +localparam G_AXI_AWQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH; +localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4; +localparam G_AXI_AWUSER_INDEX = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH; +localparam G_AXI_AWUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH; +localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH; +localparam G_AXI_ARADDR_INDEX = 0; +localparam G_AXI_ARADDR_WIDTH = C_AXI_ADDR_WIDTH; +localparam G_AXI_ARPROT_INDEX = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH; +localparam G_AXI_ARPROT_WIDTH = 3; +localparam G_AXI_ARSIZE_INDEX = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH; +localparam G_AXI_ARSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3; +localparam G_AXI_ARBURST_INDEX = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH; +localparam G_AXI_ARBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2; +localparam G_AXI_ARCACHE_INDEX = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH; +localparam G_AXI_ARCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_ARLEN_INDEX = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH; +localparam G_AXI_ARLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8; +localparam G_AXI_ARLOCK_INDEX = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH; +localparam G_AXI_ARLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1; +localparam G_AXI_ARID_INDEX = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH; +localparam G_AXI_ARID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_ARQOS_INDEX = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH; +localparam G_AXI_ARQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH; +localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4; +localparam G_AXI_ARUSER_INDEX = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH; +localparam G_AXI_ARUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH; +localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH; +// Write channel widths +localparam G_AXI_WDATA_INDEX = 0; +localparam G_AXI_WDATA_WIDTH = C_AXI_DATA_WIDTH; +localparam G_AXI_WSTRB_INDEX = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH; +localparam G_AXI_WSTRB_WIDTH = C_AXI_DATA_WIDTH / 8; +localparam G_AXI_WLAST_INDEX = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH; +localparam G_AXI_WLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1; +localparam G_AXI_WID_INDEX = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH; +localparam G_AXI_WID_WIDTH = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_WUSER_INDEX = G_AXI_WID_INDEX + G_AXI_WID_WIDTH; +localparam G_AXI_WUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH; +localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH; +// Write Response channel Widths +localparam G_AXI_BRESP_INDEX = 0; +localparam G_AXI_BRESP_WIDTH = 2; +localparam G_AXI_BID_INDEX = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH; +localparam G_AXI_BID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_BUSER_INDEX = G_AXI_BID_INDEX + G_AXI_BID_WIDTH; +localparam G_AXI_BUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH; +localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH; +// Read channel widths +localparam G_AXI_RDATA_INDEX = 0; +localparam G_AXI_RDATA_WIDTH = C_AXI_DATA_WIDTH; +localparam G_AXI_RRESP_INDEX = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH; +localparam G_AXI_RRESP_WIDTH = 2; +localparam G_AXI_RLAST_INDEX = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH; +localparam G_AXI_RLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1; +localparam G_AXI_RID_INDEX = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH; +localparam G_AXI_RID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_RUSER_INDEX = G_AXI_RID_INDEX + G_AXI_RID_WIDTH; +localparam G_AXI_RUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH; +localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH; diff --git a/hardware/XilinxAlveoU200/ddr/rtl/MigClkConvtWrapper.vhd b/hardware/XilinxAlveoU200/ddr/rtl/MigClkConvtWrapper.vhd new file mode 100644 index 0000000..bbe6edc --- /dev/null +++ b/hardware/XilinxAlveoU200/ddr/rtl/MigClkConvtWrapper.vhd @@ -0,0 +1,230 @@ +------------------------------------------------------------------------------- +-- File : MigClkConvtWrapper.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- This file is part of 'PGP PCIe APP DEV'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'PGP PCIe APP DEV', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiPkg.all; + +entity MigClkConvtWrapper is + generic ( + TPD_G : time := 1 ns); + port ( + -- USER AXI Memory Interface (axiClk domain) + axiClk : in sl; + axiRst : in sl; + axiWriteMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + axiWriteSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; + axiReadMaster : in AxiReadMasterType := AXI_READ_MASTER_INIT_C; + axiReadSlave : out AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; + -- DDR AXI Memory Interface (ddrClk domain) + ddrClk : in sl; + ddrRst : in sl; + ddrWriteMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + ddrWriteSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; + ddrReadMaster : out AxiReadMasterType := AXI_READ_MASTER_INIT_C; + ddrReadSlave : in AxiReadSlaveType := AXI_READ_SLAVE_INIT_C); +end MigClkConvtWrapper; + +architecture mapping of MigClkConvtWrapper is + + component MigClkConvt + port ( + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + s_axi_awid : in std_logic_vector (3 downto 0); + s_axi_awaddr : in std_logic_vector (63 downto 0); + s_axi_awlen : in std_logic_vector (7 downto 0); + s_axi_awsize : in std_logic_vector (2 downto 0); + s_axi_awburst : in std_logic_vector (1 downto 0); + s_axi_awlock : in std_logic_vector (0 to 0); + s_axi_awcache : in std_logic_vector (3 downto 0); + s_axi_awprot : in std_logic_vector (2 downto 0); + s_axi_awregion : in std_logic_vector (3 downto 0); + s_axi_awqos : in std_logic_vector (3 downto 0); + s_axi_awvalid : in std_logic; + s_axi_awready : out std_logic; + s_axi_wdata : in std_logic_vector (511 downto 0); + s_axi_wstrb : in std_logic_vector (63 downto 0); + s_axi_wlast : in std_logic; + s_axi_wvalid : in std_logic; + s_axi_wready : out std_logic; + s_axi_bid : out std_logic_vector (3 downto 0); + s_axi_bresp : out std_logic_vector (1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_bready : in std_logic; + s_axi_arid : in std_logic_vector (3 downto 0); + s_axi_araddr : in std_logic_vector (63 downto 0); + s_axi_arlen : in std_logic_vector (7 downto 0); + s_axi_arsize : in std_logic_vector (2 downto 0); + s_axi_arburst : in std_logic_vector (1 downto 0); + s_axi_arlock : in std_logic_vector (0 to 0); + s_axi_arcache : in std_logic_vector (3 downto 0); + s_axi_arprot : in std_logic_vector (2 downto 0); + s_axi_arregion : in std_logic_vector (3 downto 0); + s_axi_arqos : in std_logic_vector (3 downto 0); + s_axi_arvalid : in std_logic; + s_axi_arready : out std_logic; + s_axi_rid : out std_logic_vector (3 downto 0); + s_axi_rdata : out std_logic_vector (511 downto 0); + s_axi_rresp : out std_logic_vector (1 downto 0); + s_axi_rlast : out std_logic; + s_axi_rvalid : out std_logic; + s_axi_rready : in std_logic; + m_axi_aclk : in std_logic; + m_axi_aresetn : in std_logic; + m_axi_awid : out std_logic_vector (3 downto 0); + m_axi_awaddr : out std_logic_vector (63 downto 0); + m_axi_awlen : out std_logic_vector (7 downto 0); + m_axi_awsize : out std_logic_vector (2 downto 0); + m_axi_awburst : out std_logic_vector (1 downto 0); + m_axi_awlock : out std_logic_vector (0 to 0); + m_axi_awcache : out std_logic_vector (3 downto 0); + m_axi_awprot : out std_logic_vector (2 downto 0); + m_axi_awregion : out std_logic_vector (3 downto 0); + m_axi_awqos : out std_logic_vector (3 downto 0); + m_axi_awvalid : out std_logic; + m_axi_awready : in std_logic; + m_axi_wdata : out std_logic_vector (511 downto 0); + m_axi_wstrb : out std_logic_vector (63 downto 0); + m_axi_wlast : out std_logic; + m_axi_wvalid : out std_logic; + m_axi_wready : in std_logic; + m_axi_bid : in std_logic_vector (3 downto 0); + m_axi_bresp : in std_logic_vector (1 downto 0); + m_axi_bvalid : in std_logic; + m_axi_bready : out std_logic; + m_axi_arid : out std_logic_vector (3 downto 0); + m_axi_araddr : out std_logic_vector (63 downto 0); + m_axi_arlen : out std_logic_vector (7 downto 0); + m_axi_arsize : out std_logic_vector (2 downto 0); + m_axi_arburst : out std_logic_vector (1 downto 0); + m_axi_arlock : out std_logic_vector (0 to 0); + m_axi_arcache : out std_logic_vector (3 downto 0); + m_axi_arprot : out std_logic_vector (2 downto 0); + m_axi_arregion : out std_logic_vector (3 downto 0); + m_axi_arqos : out std_logic_vector (3 downto 0); + m_axi_arvalid : out std_logic; + m_axi_arready : in std_logic; + m_axi_rid : in std_logic_vector (3 downto 0); + m_axi_rdata : in std_logic_vector (511 downto 0); + m_axi_rresp : in std_logic_vector (1 downto 0); + m_axi_rlast : in std_logic; + m_axi_rvalid : in std_logic; + m_axi_rready : out std_logic); + end component; + + signal axiRstL : sl; + signal ddrRstL : sl; + +begin + + axiRstL <= not(axiRst); + ddrRstL <= not(ddrRst); + + ------------------------ + -- MIG + ------------------------ + U_Clk_Convt : MigClkConvt + port map ( + -- Slave Ports + s_axi_aclk => axiClk, + s_axi_aresetn => axiRstL, + s_axi_awid => axiWriteMaster.awid(3 downto 0), + s_axi_awaddr => axiWriteMaster.awaddr(63 downto 0), + s_axi_awlen => axiWriteMaster.awlen(7 downto 0), + s_axi_awsize => axiWriteMaster.awsize(2 downto 0), + s_axi_awburst => axiWriteMaster.awburst(1 downto 0), + s_axi_awlock => axiWriteMaster.awlock(0 downto 0), + s_axi_awcache => axiWriteMaster.awcache(3 downto 0), + s_axi_awprot => axiWriteMaster.awprot(2 downto 0), + s_axi_awregion => axiWriteMaster.awregion(3 downto 0), + s_axi_awqos => axiWriteMaster.awqos(3 downto 0), + s_axi_awvalid => axiWriteMaster.awvalid, + s_axi_awready => axiWriteSlave.awready, + s_axi_wdata => axiWriteMaster.wdata(511 downto 0), + s_axi_wstrb => axiWriteMaster.wstrb(63 downto 0), + s_axi_wlast => axiWriteMaster.wlast, + s_axi_wvalid => axiWriteMaster.wvalid, + s_axi_wready => axiWriteSlave.wready, + s_axi_bid => axiWriteSlave.bid(3 downto 0), + s_axi_bresp => axiWriteSlave.bresp(1 downto 0), + s_axi_bvalid => axiWriteSlave.bvalid, + s_axi_bready => axiWriteMaster.bready, + s_axi_arid => axiReadMaster.arid(3 downto 0), + s_axi_araddr => axiReadMaster.araddr(63 downto 0), + s_axi_arlen => axiReadMaster.arlen(7 downto 0), + s_axi_arsize => axiReadMaster.arsize(2 downto 0), + s_axi_arburst => axiReadMaster.arburst(1 downto 0), + s_axi_arlock => axiReadMaster.arlock(0 downto 0), + s_axi_arcache => axiReadMaster.arcache(3 downto 0), + s_axi_arprot => axiReadMaster.arprot(2 downto 0), + s_axi_arregion => axiReadMaster.arregion(3 downto 0), + s_axi_arqos => axiReadMaster.arqos(3 downto 0), + s_axi_arvalid => axiReadMaster.arvalid, + s_axi_arready => axiReadSlave.arready, + s_axi_rid => axiReadSlave.rid(3 downto 0), + s_axi_rdata => axiReadSlave.rdata(511 downto 0), + s_axi_rresp => axiReadSlave.rresp(1 downto 0), + s_axi_rlast => axiReadSlave.rlast, + s_axi_rvalid => axiReadSlave.rvalid, + s_axi_rready => axiReadMaster.rready, + -- Master Ports + m_axi_aclk => ddrClk, + m_axi_aresetn => ddrRstL, + m_axi_awid => ddrWriteMaster.awid(3 downto 0), + m_axi_awaddr => ddrWriteMaster.awaddr(63 downto 0), + m_axi_awlen => ddrWriteMaster.awlen(7 downto 0), + m_axi_awsize => ddrWriteMaster.awsize(2 downto 0), + m_axi_awburst => ddrWriteMaster.awburst(1 downto 0), + m_axi_awlock => ddrWriteMaster.awlock(0 downto 0), + m_axi_awcache => ddrWriteMaster.awcache(3 downto 0), + m_axi_awprot => ddrWriteMaster.awprot(2 downto 0), + m_axi_awregion => ddrWriteMaster.awregion(3 downto 0), + m_axi_awqos => ddrWriteMaster.awqos(3 downto 0), + m_axi_awvalid => ddrWriteMaster.awvalid, + m_axi_awready => ddrWriteSlave.awready, + m_axi_wdata => ddrWriteMaster.wdata(511 downto 0), + m_axi_wstrb => ddrWriteMaster.wstrb(63 downto 0), + m_axi_wlast => ddrWriteMaster.wlast, + m_axi_wvalid => ddrWriteMaster.wvalid, + m_axi_wready => ddrWriteSlave.wready, + m_axi_bid => ddrWriteSlave.bid(3 downto 0), + m_axi_bresp => ddrWriteSlave.bresp(1 downto 0), + m_axi_bvalid => ddrWriteSlave.bvalid, + m_axi_bready => ddrWriteMaster.bready, + m_axi_arid => ddrReadMaster.arid(3 downto 0), + m_axi_araddr => ddrReadMaster.araddr(63 downto 0), + m_axi_arlen => ddrReadMaster.arlen(7 downto 0), + m_axi_arsize => ddrReadMaster.arsize(2 downto 0), + m_axi_arburst => ddrReadMaster.arburst(1 downto 0), + m_axi_arlock => ddrReadMaster.arlock(0 downto 0), + m_axi_arcache => ddrReadMaster.arcache(3 downto 0), + m_axi_arprot => ddrReadMaster.arprot(2 downto 0), + m_axi_arregion => ddrReadMaster.arregion(3 downto 0), + m_axi_arqos => ddrReadMaster.arqos(3 downto 0), + m_axi_arvalid => ddrReadMaster.arvalid, + m_axi_arready => ddrReadSlave.arready, + m_axi_rid => ddrReadSlave.rid(3 downto 0), + m_axi_rdata => ddrReadSlave.rdata(511 downto 0), + m_axi_rresp => ddrReadSlave.rresp(1 downto 0), + m_axi_rlast => ddrReadSlave.rlast, + m_axi_rvalid => ddrReadSlave.rvalid, + m_axi_rready => ddrReadMaster.rready); + +end mapping; diff --git a/hardware/XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd b/hardware/XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd index d91a0cb..303f08c 100644 --- a/hardware/XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd +++ b/hardware/XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd @@ -61,22 +61,19 @@ end MigDmaBuffer; architecture mapping of MigDmaBuffer is constant AXI_BUFFER_WIDTH_C : positive := MEM_AXI_CONFIG_C.ADDR_WIDTH_C-1; -- 1 DDR DIMM split between 2 DMA lanes - constant AXI_BASE_ADDR_C : Slv64Array(1 downto 0) := ( - 0 => toSlv(0, 64), - 1 => toSlv(2**AXI_BUFFER_WIDTH_C, 64)); -- Units of bytes - - constant INT_DMA_AXIS_CONFIG_C : AxiStreamConfigType := ( - TSTRB_EN_C => false, - TDATA_BYTES_C => DMA_AXIS_CONFIG_G.TDATA_BYTES_C, - TDEST_BITS_C => 8, - TID_BITS_C => 3, - TKEEP_MODE_C => TKEEP_COUNT_C, -- AXI DMA V2 uses TKEEP_COUNT_C to help meet timing - TUSER_BITS_C => 4, - TUSER_MODE_C => TUSER_FIRST_LAST_C); + constant AXI_BASE_ADDR_C : Slv64Array(7 downto 0) := ( + 0 => x"0000_0000_0000_0000", + 1 => x"0000_0002_0000_0000", + 2 => x"0000_0000_0000_0000", + 3 => x"0000_0002_0000_0000", + 4 => x"0000_0000_0000_0000", + 5 => x"0000_0002_0000_0000", + 6 => x"0000_0000_0000_0000", + 7 => x"0000_0002_0000_0000"); constant DMA_AXI_CONFIG_C : AxiConfigType := ( ADDR_WIDTH_C => 40, -- Match 40-bit address for axi_pcie_core.AxiPcieCrossbar - DATA_BYTES_C => INT_DMA_AXIS_CONFIG_C.TDATA_BYTES_C, -- Matches the AXIS stream + DATA_BYTES_C => DMA_AXIS_CONFIG_G.TDATA_BYTES_C, -- Matches the AXIS stream ID_BITS_C => MEM_AXI_CONFIG_C.ID_BITS_C, LEN_BITS_C => MEM_AXI_CONFIG_C.LEN_BITS_C); @@ -103,23 +100,29 @@ architecture mapping of MigDmaBuffer is signal unusedReadMasters : AxiReadMasterArray(7 downto 0) := (others => AXI_READ_MASTER_INIT_C); signal unusedReadSlaves : AxiReadSlaveArray(7 downto 0) := (others => AXI_READ_SLAVE_INIT_C); - signal sAxisCtrl : AxiStreamCtrlArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_CTRL_INIT_C); + signal syncWriteMasters : AxiWriteMasterArray(7 downto 0) := (others => AXI_WRITE_MASTER_INIT_C); + signal syncWriteSlaves : AxiWriteSlaveArray(7 downto 0) := (others => AXI_WRITE_SLAVE_INIT_C); + signal syncReadMasters : AxiReadMasterArray(7 downto 0) := (others => AXI_READ_MASTER_INIT_C); + signal syncReadSlaves : AxiReadSlaveArray(7 downto 0) := (others => AXI_READ_SLAVE_INIT_C); - signal rxMasters : AxiStreamMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal rxSlaves : AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); - signal txMasters : AxiStreamMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal txSlaves : AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + signal sAxisCtrl : AxiStreamCtrlArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_CTRL_INIT_C); - signal ddrClock : slv(7 downto 0); - signal ddrReset : slv(7 downto 0); signal ddrRdy : slv(7 downto 0); - signal axisReset : slv(7 downto 0); + signal axiReady : slv(7 downto 0); + signal axisReset : slv(DMA_SIZE_G-1 downto 0); + signal axiReset : slv(3 downto 0); begin - ddrClock <= ddrClk(3) & ddrClk(3) & ddrClk(2) & ddrClk(2) & ddrClk(1) & ddrClk(1) & ddrClk(0) & ddrClk(0); - ddrReset <= ddrRst(3) & ddrRst(3) & ddrRst(2) & ddrRst(2) & ddrRst(1) & ddrRst(1) & ddrRst(0) & ddrRst(0); - ddrRdy <= ddrReady(3) & ddrReady(3) & ddrReady(2) & ddrReady(2) & ddrReady(1) & ddrReady(1) & ddrReady(0) & ddrReady(0); + ddrRdy <= ddrReady(3) & ddrReady(3) & ddrReady(2) & ddrReady(2) & ddrReady(1) & ddrReady(1) & ddrReady(0) & ddrReady(0); + U_axiReady : entity surf.SynchronizerVector + generic map ( + TPD_G => TPD_G, + WIDTH_G => 8) + port map ( + clk => axisClk, + dataIn => ddrRdy, + dataOut => axiReady); -------------------- -- AXI-Lite Crossbar @@ -154,33 +157,13 @@ begin rstIn => axisRst, rstOut => axisReset(i)); - -------------------------- - -- Inbound AXI Stream FIFO - -------------------------- - U_IbFifo : entity surf.AxiStreamFifoV2 + U_pause : entity surf.Synchronizer generic map ( - -- General Configurations - TPD_G => TPD_G, - SLAVE_READY_EN_G => true, - VALID_THOLD_G => 1, - -- FIFO configurations - MEMORY_TYPE_G => "block", - GEN_SYNC_FIFO_G => false, - FIFO_ADDR_WIDTH_G => 9, - -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G => DMA_AXIS_CONFIG_G, - MASTER_AXI_CONFIG_G => INT_DMA_AXIS_CONFIG_C) + TPD_G => TPD_G) port map ( - -- Slave Port - sAxisClk => axisClk, - sAxisRst => axisReset(i), - sAxisMaster => sAxisMasters(i), - sAxisSlave => sAxisSlaves(i), - -- Master Port - mAxisClk => ddrClock(i), - mAxisRst => ddrReset(i), - mAxisMaster => rxMasters(i), - mAxisSlave => rxSlaves(i)); + clk => eventClk, + dataIn => sAxisCtrl(i).pause, + dataOut => eventTrigMsgCtrl(i).pause); U_AxiFifo : entity surf.AxiStreamDmaV2Fifo generic map ( @@ -191,25 +174,25 @@ begin SYNTH_MODE_G => "xpm", MEMORY_TYPE_G => "ultra", -- AXI Stream Configurations - AXIS_CONFIG_G => INT_DMA_AXIS_CONFIG_C, + AXIS_CONFIG_G => DMA_AXIS_CONFIG_G, -- AXI4 Configurations - AXI_BASE_ADDR_G => AXI_BASE_ADDR_C(i mod 2), + AXI_BASE_ADDR_G => AXI_BASE_ADDR_C(i), AXI_CONFIG_G => DMA_AXI_CONFIG_C) port map ( -- AXI4 Interface (axiClk domain) - axiClk => ddrClock(i), - axiRst => ddrReset(i), - axiReady => ddrRdy(i), + axiClk => axisClk, + axiRst => axisReset(i), + axiReady => axiReady(i), axiReadMaster => axiReadMasters(i), axiReadSlave => axiReadSlaves(i), axiWriteMaster => axiWriteMasters(i), axiWriteSlave => axiWriteSlaves(i), -- AXI Stream Interface (axiClk domain) - sAxisMaster => rxMasters(i), - sAxisSlave => rxSlaves(i), + sAxisMaster => sAxisMasters(i), + sAxisSlave => sAxisSlaves(i), sAxisCtrl => sAxisCtrl(i), - mAxisMaster => txMasters(i), - mAxisSlave => txSlaves(i), + mAxisMaster => mAxisMasters(i), + mAxisSlave => mAxisSlaves(i), -- Optional: AXI-Lite Interface (axilClk domain) axilClk => axilClk, axilRst => axilRst, @@ -218,42 +201,20 @@ begin axilWriteMaster => axilWriteMasters(i), axilWriteSlave => axilWriteSlaves(i)); - U_pause : entity surf.Synchronizer - generic map ( - TPD_G => TPD_G) - port map ( - clk => eventClk, - dataIn => sAxisCtrl(i).pause, - dataOut => eventTrigMsgCtrl(i).pause); + end generate; + + GEN_XBAR : for i in 3 downto 0 generate - U_ObFifo : entity surf.AxiStreamFifoV2 + -- Help with timing + U_AxiRst : entity surf.RstPipeline generic map ( - -- General Configurations - TPD_G => TPD_G, - SLAVE_READY_EN_G => true, - VALID_THOLD_G => 1, - -- FIFO configurations - MEMORY_TYPE_G => "block", - GEN_SYNC_FIFO_G => false, - FIFO_ADDR_WIDTH_G => 9, - -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G => INT_DMA_AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => DMA_AXIS_CONFIG_G) + TPD_G => TPD_G, + INV_RST_G => false) port map ( - -- Slave Port - sAxisClk => ddrClock(i), - sAxisRst => ddrReset(i), - sAxisMaster => txMasters(i), - sAxisSlave => txSlaves(i), - -- Master Port - mAxisClk => axisClk, - mAxisRst => axisReset(i), - mAxisMaster => mAxisMasters(i), - mAxisSlave => mAxisSlaves(i)); - - end generate; + clk => axisClk, + rstIn => axisRst, + rstOut => axiReset(i)); - GEN_XBAR : for i in 3 downto 0 generate -- Reuse the AxiPcieCrossbar for the MIGT DMA Buffer U_XBAR : entity axi_pcie_core.AxiPcieCrossbar generic map ( @@ -262,8 +223,8 @@ begin AXI_PCIE_CONFIG_G => INT_DMA_AXI_CONFIG_C, DMA_SIZE_G => 2) port map ( - axiClk => ddrClk(i), - axiRst => ddrRst(i), + axiClk => axisClk, + axiRst => axiReset(i), -- Slave Write Masters sAxiWriteMasters(3) => unusedWriteMasters(i+4), -- General Purpose AXI path sAxiWriteMasters(2 downto 1) => axiWriteMasters(2*i+1 downto 2*i), @@ -281,10 +242,30 @@ begin sAxiReadSlaves(2 downto 1) => axiReadSlaves(2*i+1 downto 2*i), sAxiReadSlaves(0) => unusedReadSlaves(i+0), -- PIP path -- Master - mAxiWriteMaster => ddrWriteMasters(i), - mAxiWriteSlave => ddrWriteSlaves(i), - mAxiReadMaster => ddrReadMasters(i), - mAxiReadSlave => ddrReadSlaves(i)); + mAxiWriteMaster => syncWriteMasters(i), + mAxiWriteSlave => syncWriteSlaves(i), + mAxiReadMaster => syncReadMasters(i), + mAxiReadSlave => syncReadSlaves(i)); + + U_DdrSync : entity axi_pcie_core.MigClkConvtWrapper + generic map ( + TPD_G => TPD_G) + port map ( + -- USER AXI Memory Interface (axiClk domain) + axiClk => axisClk, + axiRst => axiReset(i), + axiWriteMaster => syncWriteMasters(i), + axiWriteSlave => syncWriteSlaves(i), + axiReadMaster => syncReadMasters(i), + axiReadSlave => syncReadSlaves(i), + -- DDR AXI Memory Interface (ddrClk domain) + ddrClk => ddrClk(i), + ddrRst => ddrRst(i), + ddrWriteMaster => ddrWriteMasters(i), + ddrWriteSlave => ddrWriteSlaves(i), + ddrReadMaster => ddrReadMasters(i), + ddrReadSlave => ddrReadSlaves(i)); + end generate; end mapping; diff --git a/hardware/XilinxAlveoU200/ddr/ruckus.tcl b/hardware/XilinxAlveoU200/ddr/ruckus.tcl index d180773..ceab30a 100644 --- a/hardware/XilinxAlveoU200/ddr/ruckus.tcl +++ b/hardware/XilinxAlveoU200/ddr/ruckus.tcl @@ -7,6 +7,9 @@ loadIpCore -dir "$::DIR_PATH/ip" loadSource -lib axi_pcie_core -sim_only -dir "$::DIR_PATH/tb" loadConstraints -dir "$::DIR_PATH/xdc" +# Add MigClkConvt dependent header for simulation +loadSource -sim_only -lib axi_infrastructure_v1_1_0 -fileType {Verilog Header} -path "$::DIR_PATH/ip/axi_infrastructure_v1_1_0.vh" + # Load the User port naming loadConstraints -path "$::DIR_PATH/xdc/XilinxAlveoU200Mig0_user_mapping.xdc" set_property USED_IN {synthesis implementation board} [get_files {XilinxAlveoU200Mig0_user_mapping.xdc}] diff --git a/hardware/XilinxAlveoU200/ddr/xdc/XilinxAlveoU200MigTiming.xdc b/hardware/XilinxAlveoU200/ddr/xdc/XilinxAlveoU200MigTiming.xdc index 5b57f31..b7833fc 100644 --- a/hardware/XilinxAlveoU200/ddr/xdc/XilinxAlveoU200MigTiming.xdc +++ b/hardware/XilinxAlveoU200/ddr/xdc/XilinxAlveoU200MigTiming.xdc @@ -8,6 +8,30 @@ ## the terms contained in the LICENSE.txt file. ############################################################################## +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_Mig/U_Mig0}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_MigDmaBuffer/GEN_FIFO[0].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_MigDmaBuffer/GEN_FIFO[1].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_MigDmaBuffer/GEN_XBAR[0].U_DdrSync}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_MigDmaBuffer/GEN_XBAR[0].U_XBAR}] + +set_property USER_SLR_ASSIGNMENT SLR2 [get_cells {U_Mig/GEN_MIG1.U_Mig1}] +set_property USER_SLR_ASSIGNMENT SLR2 [get_cells {U_MigDmaBuffer/GEN_FIFO[2].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR2 [get_cells {U_MigDmaBuffer/GEN_FIFO[3].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR2 [get_cells {U_MigDmaBuffer/GEN_XBAR[1].U_DdrSync}] +set_property USER_SLR_ASSIGNMENT SLR2 [get_cells {U_MigDmaBuffer/GEN_XBAR[1].U_XBAR}] + +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_Mig/GEN_MIG1.U_Mig2}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_FIFO[4].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_FIFO[5].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_XBAR[2].U_DdrSync}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_XBAR[2].U_XBAR}] + +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_Mig/GEN_MIG1.U_Mig3}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_FIFO[6].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_FIFO[7].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_XBAR[3].U_DdrSync}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_XBAR[3].U_XBAR}] + set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {ddrClkP[0]}] -group [get_clocks -include_generated_clocks {pciRefClkP}] set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {ddrClkP[1]}] -group [get_clocks -include_generated_clocks {pciRefClkP}] set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {ddrClkP[2]}] -group [get_clocks -include_generated_clocks {pciRefClkP}] diff --git a/hardware/XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd b/hardware/XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd index c65a322..5b34da0 100644 --- a/hardware/XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd +++ b/hardware/XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd @@ -61,22 +61,19 @@ end MigDmaBuffer; architecture mapping of MigDmaBuffer is constant AXI_BUFFER_WIDTH_C : positive := MEM_AXI_CONFIG_C.ADDR_WIDTH_C-1; -- 1 DDR DIMM split between 2 DMA lanes - constant AXI_BASE_ADDR_C : Slv64Array(1 downto 0) := ( - 0 => toSlv(0, 64), - 1 => toSlv(2**AXI_BUFFER_WIDTH_C, 64)); -- Units of bytes - - constant INT_DMA_AXIS_CONFIG_C : AxiStreamConfigType := ( - TSTRB_EN_C => false, - TDATA_BYTES_C => DMA_AXIS_CONFIG_G.TDATA_BYTES_C, - TDEST_BITS_C => 8, - TID_BITS_C => 3, - TKEEP_MODE_C => TKEEP_COUNT_C, -- AXI DMA V2 uses TKEEP_COUNT_C to help meet timing - TUSER_BITS_C => 4, - TUSER_MODE_C => TUSER_FIRST_LAST_C); + constant AXI_BASE_ADDR_C : Slv64Array(7 downto 0) := ( + 0 => x"0000_0000_0000_0000", + 1 => x"0000_0000_8000_0000", + 2 => x"0000_0000_0000_0000", + 3 => x"0000_0000_8000_0000", + 4 => x"0000_0000_0000_0000", + 5 => x"0000_0000_8000_0000", + 6 => x"0000_0000_0000_0000", + 7 => x"0000_0000_8000_0000"); constant DMA_AXI_CONFIG_C : AxiConfigType := ( ADDR_WIDTH_C => 40, -- Match 40-bit address for axi_pcie_core.AxiPcieCrossbar - DATA_BYTES_C => INT_DMA_AXIS_CONFIG_C.TDATA_BYTES_C, -- Matches the AXIS stream + DATA_BYTES_C => DMA_AXIS_CONFIG_G.TDATA_BYTES_C, -- Matches the AXIS stream ID_BITS_C => MEM_AXI_CONFIG_C.ID_BITS_C, LEN_BITS_C => MEM_AXI_CONFIG_C.LEN_BITS_C); @@ -103,23 +100,29 @@ architecture mapping of MigDmaBuffer is signal unusedReadMasters : AxiReadMasterArray(7 downto 0) := (others => AXI_READ_MASTER_INIT_C); signal unusedReadSlaves : AxiReadSlaveArray(7 downto 0) := (others => AXI_READ_SLAVE_INIT_C); - signal sAxisCtrl : AxiStreamCtrlArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_CTRL_INIT_C); + signal syncWriteMasters : AxiWriteMasterArray(7 downto 0) := (others => AXI_WRITE_MASTER_INIT_C); + signal syncWriteSlaves : AxiWriteSlaveArray(7 downto 0) := (others => AXI_WRITE_SLAVE_INIT_C); + signal syncReadMasters : AxiReadMasterArray(7 downto 0) := (others => AXI_READ_MASTER_INIT_C); + signal syncReadSlaves : AxiReadSlaveArray(7 downto 0) := (others => AXI_READ_SLAVE_INIT_C); - signal rxMasters : AxiStreamMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal rxSlaves : AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); - signal txMasters : AxiStreamMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal txSlaves : AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + signal sAxisCtrl : AxiStreamCtrlArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_CTRL_INIT_C); - signal ddrClock : slv(7 downto 0); - signal ddrReset : slv(7 downto 0); signal ddrRdy : slv(7 downto 0); - signal axisReset : slv(7 downto 0); + signal axiReady : slv(7 downto 0); + signal axisReset : slv(DMA_SIZE_G-1 downto 0); + signal axiReset : slv(3 downto 0); begin - ddrClock <= ddrClk(3) & ddrClk(3) & ddrClk(2) & ddrClk(2) & ddrClk(1) & ddrClk(1) & ddrClk(0) & ddrClk(0); - ddrReset <= ddrRst(3) & ddrRst(3) & ddrRst(2) & ddrRst(2) & ddrRst(1) & ddrRst(1) & ddrRst(0) & ddrRst(0); - ddrRdy <= ddrReady(3) & ddrReady(3) & ddrReady(2) & ddrReady(2) & ddrReady(1) & ddrReady(1) & ddrReady(0) & ddrReady(0); + ddrRdy <= ddrReady(3) & ddrReady(3) & ddrReady(2) & ddrReady(2) & ddrReady(1) & ddrReady(1) & ddrReady(0) & ddrReady(0); + U_axiReady : entity surf.SynchronizerVector + generic map ( + TPD_G => TPD_G, + WIDTH_G => 8) + port map ( + clk => axisClk, + dataIn => ddrRdy, + dataOut => axiReady); -------------------- -- AXI-Lite Crossbar @@ -154,33 +157,13 @@ begin rstIn => axisRst, rstOut => axisReset(i)); - -------------------------- - -- Inbound AXI Stream FIFO - -------------------------- - U_IbFifo : entity surf.AxiStreamFifoV2 + U_pause : entity surf.Synchronizer generic map ( - -- General Configurations - TPD_G => TPD_G, - SLAVE_READY_EN_G => true, - VALID_THOLD_G => 1, - -- FIFO configurations - MEMORY_TYPE_G => "block", - GEN_SYNC_FIFO_G => false, - FIFO_ADDR_WIDTH_G => 9, - -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G => DMA_AXIS_CONFIG_G, - MASTER_AXI_CONFIG_G => INT_DMA_AXIS_CONFIG_C) + TPD_G => TPD_G) port map ( - -- Slave Port - sAxisClk => axisClk, - sAxisRst => axisReset(i), - sAxisMaster => sAxisMasters(i), - sAxisSlave => sAxisSlaves(i), - -- Master Port - mAxisClk => ddrClock(i), - mAxisRst => ddrReset(i), - mAxisMaster => rxMasters(i), - mAxisSlave => rxSlaves(i)); + clk => eventClk, + dataIn => sAxisCtrl(i).pause, + dataOut => eventTrigMsgCtrl(i).pause); U_AxiFifo : entity surf.AxiStreamDmaV2Fifo generic map ( @@ -191,25 +174,25 @@ begin SYNTH_MODE_G => "xpm", MEMORY_TYPE_G => "block", -- AXI Stream Configurations - AXIS_CONFIG_G => INT_DMA_AXIS_CONFIG_C, + AXIS_CONFIG_G => DMA_AXIS_CONFIG_G, -- AXI4 Configurations - AXI_BASE_ADDR_G => AXI_BASE_ADDR_C(i mod 2), + AXI_BASE_ADDR_G => AXI_BASE_ADDR_C(i), AXI_CONFIG_G => DMA_AXI_CONFIG_C) port map ( -- AXI4 Interface (axiClk domain) - axiClk => ddrClock(i), - axiRst => ddrReset(i), - axiReady => ddrRdy(i), + axiClk => axisClk, + axiRst => axisReset(i), + axiReady => axiReady(i), axiReadMaster => axiReadMasters(i), axiReadSlave => axiReadSlaves(i), axiWriteMaster => axiWriteMasters(i), axiWriteSlave => axiWriteSlaves(i), -- AXI Stream Interface (axiClk domain) - sAxisMaster => rxMasters(i), - sAxisSlave => rxSlaves(i), + sAxisMaster => sAxisMasters(i), + sAxisSlave => sAxisSlaves(i), sAxisCtrl => sAxisCtrl(i), - mAxisMaster => txMasters(i), - mAxisSlave => txSlaves(i), + mAxisMaster => mAxisMasters(i), + mAxisSlave => mAxisSlaves(i), -- Optional: AXI-Lite Interface (axilClk domain) axilClk => axilClk, axilRst => axilRst, @@ -218,43 +201,21 @@ begin axilWriteMaster => axilWriteMasters(i), axilWriteSlave => axilWriteSlaves(i)); - U_pause : entity surf.Synchronizer - generic map ( - TPD_G => TPD_G) - port map ( - clk => eventClk, - dataIn => sAxisCtrl(i).pause, - dataOut => eventTrigMsgCtrl(i).pause); + end generate; + + GEN_XBAR : for i in 3 downto 0 generate - U_ObFifo : entity surf.AxiStreamFifoV2 + -- Help with timing + U_AxiRst : entity surf.RstPipeline generic map ( - -- General Configurations - TPD_G => TPD_G, - SLAVE_READY_EN_G => true, - VALID_THOLD_G => 1, - -- FIFO configurations - MEMORY_TYPE_G => "block", - GEN_SYNC_FIFO_G => false, - FIFO_ADDR_WIDTH_G => 9, - -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G => INT_DMA_AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => DMA_AXIS_CONFIG_G) + TPD_G => TPD_G, + INV_RST_G => false) port map ( - -- Slave Port - sAxisClk => ddrClock(i), - sAxisRst => ddrReset(i), - sAxisMaster => txMasters(i), - sAxisSlave => txSlaves(i), - -- Master Port - mAxisClk => axisClk, - mAxisRst => axisReset(i), - mAxisMaster => mAxisMasters(i), - mAxisSlave => mAxisSlaves(i)); - - end generate; + clk => axisClk, + rstIn => axisRst, + rstOut => axiReset(i)); - GEN_XBAR : for i in 3 downto 0 generate - -- Reuse the AxiPcieCrossbar for the MIG DMA Buffer + -- Reuse the AxiPcieCrossbar for the MIGT DMA Buffer U_XBAR : entity axi_pcie_core.AxiPcieCrossbar generic map ( TPD_G => TPD_G, @@ -262,8 +223,8 @@ begin AXI_PCIE_CONFIG_G => INT_DMA_AXI_CONFIG_C, DMA_SIZE_G => 2) port map ( - axiClk => ddrClk(i), - axiRst => ddrRst(i), + axiClk => axisClk, + axiRst => axiReset(i), -- Slave Write Masters sAxiWriteMasters(3) => unusedWriteMasters(i+4), -- General Purpose AXI path sAxiWriteMasters(2 downto 1) => axiWriteMasters(2*i+1 downto 2*i), @@ -281,10 +242,30 @@ begin sAxiReadSlaves(2 downto 1) => axiReadSlaves(2*i+1 downto 2*i), sAxiReadSlaves(0) => unusedReadSlaves(i+0), -- PIP path -- Master - mAxiWriteMaster => ddrWriteMasters(i), - mAxiWriteSlave => ddrWriteSlaves(i), - mAxiReadMaster => ddrReadMasters(i), - mAxiReadSlave => ddrReadSlaves(i)); + mAxiWriteMaster => syncWriteMasters(i), + mAxiWriteSlave => syncWriteSlaves(i), + mAxiReadMaster => syncReadMasters(i), + mAxiReadSlave => syncReadSlaves(i)); + + U_DdrSync : entity axi_pcie_core.MigClkConvtWrapper + generic map ( + TPD_G => TPD_G) + port map ( + -- USER AXI Memory Interface (axiClk domain) + axiClk => axisClk, + axiRst => axiReset(i), + axiWriteMaster => syncWriteMasters(i), + axiWriteSlave => syncWriteSlaves(i), + axiReadMaster => syncReadMasters(i), + axiReadSlave => syncReadSlaves(i), + -- DDR AXI Memory Interface (ddrClk domain) + ddrClk => ddrClk(i), + ddrRst => ddrRst(i), + ddrWriteMaster => ddrWriteMasters(i), + ddrWriteSlave => ddrWriteSlaves(i), + ddrReadMaster => ddrReadMasters(i), + ddrReadSlave => ddrReadSlaves(i)); + end generate; end mapping; diff --git a/hardware/XilinxKcu1500/ddr/xdc/XilinxKcu1500MigTiming.xdc b/hardware/XilinxKcu1500/ddr/xdc/XilinxKcu1500MigTiming.xdc index 5b57f31..a2dd764 100644 --- a/hardware/XilinxKcu1500/ddr/xdc/XilinxKcu1500MigTiming.xdc +++ b/hardware/XilinxKcu1500/ddr/xdc/XilinxKcu1500MigTiming.xdc @@ -8,6 +8,30 @@ ## the terms contained in the LICENSE.txt file. ############################################################################## +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_Mig/U_Mig0}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_MigDmaBuffer/GEN_FIFO[0].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_MigDmaBuffer/GEN_FIFO[1].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_MigDmaBuffer/GEN_XBAR[0].U_DdrSync}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_MigDmaBuffer/GEN_XBAR[0].U_XBAR}] + +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_Mig/GEN_MIG1.U_Mig1}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_MigDmaBuffer/GEN_FIFO[2].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_MigDmaBuffer/GEN_FIFO[3].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_MigDmaBuffer/GEN_XBAR[1].U_DdrSync}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_MigDmaBuffer/GEN_XBAR[1].U_XBAR}] + +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_Mig/GEN_MIG1.U_Mig2}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_FIFO[4].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_FIFO[5].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_XBAR[2].U_DdrSync}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_XBAR[2].U_XBAR}] + +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_Mig/GEN_MIG1.U_Mig3}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_FIFO[6].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_FIFO[7].U_AxiFifo}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_XBAR[3].U_DdrSync}] +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {U_MigDmaBuffer/GEN_XBAR[3].U_XBAR}] + set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {ddrClkP[0]}] -group [get_clocks -include_generated_clocks {pciRefClkP}] set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {ddrClkP[1]}] -group [get_clocks -include_generated_clocks {pciRefClkP}] set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {ddrClkP[2]}] -group [get_clocks -include_generated_clocks {pciRefClkP}] From 4e9a5ee77bf68895f16dce82fa42c884745fe0b6 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 29 Jun 2022 15:53:40 -0700 Subject: [PATCH 3/3] adding HbmDmaBuffer.vhd --- .../XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd | 2 +- .../XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd | 2 +- .../pcie-3x16/ip/HbmDmaBufferIpCore.xci | 8168 +++++++++++++++++ .../pcie-3x16/rtl/HbmDmaBuffer.vhd | 834 ++ .../XilinxVariumC1100/pcie-3x16/ruckus.tcl | 3 +- shared/ruckus.tcl | 4 +- 6 files changed, 9008 insertions(+), 5 deletions(-) create mode 100644 hardware/XilinxVariumC1100/pcie-3x16/ip/HbmDmaBufferIpCore.xci create mode 100644 hardware/XilinxVariumC1100/pcie-3x16/rtl/HbmDmaBuffer.vhd diff --git a/hardware/XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd b/hardware/XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd index 303f08c..eb415a3 100644 --- a/hardware/XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd +++ b/hardware/XilinxAlveoU200/ddr/rtl/MigDmaBuffer.vhd @@ -73,7 +73,7 @@ architecture mapping of MigDmaBuffer is constant DMA_AXI_CONFIG_C : AxiConfigType := ( ADDR_WIDTH_C => 40, -- Match 40-bit address for axi_pcie_core.AxiPcieCrossbar - DATA_BYTES_C => DMA_AXIS_CONFIG_G.TDATA_BYTES_C, -- Matches the AXIS stream + DATA_BYTES_C => DMA_AXIS_CONFIG_G.TDATA_BYTES_C, -- Matches the AXIS stream because you ***CANNOT*** resize an interleaved AXI stream ID_BITS_C => MEM_AXI_CONFIG_C.ID_BITS_C, LEN_BITS_C => MEM_AXI_CONFIG_C.LEN_BITS_C); diff --git a/hardware/XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd b/hardware/XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd index 5b34da0..8a8781d 100644 --- a/hardware/XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd +++ b/hardware/XilinxKcu1500/ddr/rtl/MigDmaBuffer.vhd @@ -73,7 +73,7 @@ architecture mapping of MigDmaBuffer is constant DMA_AXI_CONFIG_C : AxiConfigType := ( ADDR_WIDTH_C => 40, -- Match 40-bit address for axi_pcie_core.AxiPcieCrossbar - DATA_BYTES_C => DMA_AXIS_CONFIG_G.TDATA_BYTES_C, -- Matches the AXIS stream + DATA_BYTES_C => DMA_AXIS_CONFIG_G.TDATA_BYTES_C, -- Matches the AXIS stream because you ***CANNOT*** resize an interleaved AXI stream ID_BITS_C => MEM_AXI_CONFIG_C.ID_BITS_C, LEN_BITS_C => MEM_AXI_CONFIG_C.LEN_BITS_C); diff --git a/hardware/XilinxVariumC1100/pcie-3x16/ip/HbmDmaBufferIpCore.xci b/hardware/XilinxVariumC1100/pcie-3x16/ip/HbmDmaBufferIpCore.xci new file mode 100644 index 0000000..7320e72 --- /dev/null +++ b/hardware/XilinxVariumC1100/pcie-3x16/ip/HbmDmaBufferIpCore.xci @@ -0,0 +1,8168 @@ + + + xilinx.com + xci + unknown + 1.0 + + + HbmDmaBufferIpCore + + + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 0 + 0 + 0 + + 256 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 450 + 450 + 16 + 2 + FALSE + FALSE + FALSE + TRUE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + TRUE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + 1800 + 1800 + 900 + 900 + 100 + 100 + 2 + 0 + FALSE + 10000000 + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + 75 + 75 + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + true + true + true + true + true + true + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + TRUE + TRUE + 1 + 1 + 100000 + 100000 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + HbmDmaBufferIpCore + 2 + 1 + 9 + 2 + 1 + 9 + 9 + 2 + 2 + 2 + 2 + 2 + 2 + 1 + false + 100 + 100 + 10.0 + 10.0 + yes + 32 + 450 + 450 + 100 + 10.000 + 10000 + 10.000 + 100 + 10.000 + 10000 + 10.000 + UC1899 + 100 + 10 + 10 + 10 + 10 + 10 + 10 + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + AXI_03_ACLK + AXI_16_ACLK + MULTIPLE + Controller_and_Physical_Layer + FALSE + 450.000 + 450.000 + FALSE + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + FALSE + FALSE + FALSE + NON_SYNTHESIZABLE + 2 + 2 + 6 + 6 + 8GB + 36 + 36 + 0x00000000 + 0x00000000 + 0x0000A600 + 0x0000A600 + 0x00000902 + 0x00000902 + 0x00000000 + 0x00000000 + 0x00001f1f + 0x00001f1f + 3 + 3 + 1000 + 1000 + 31 + 31 + 31 + 31 + 10 + 10 + 450 + 450 + 100 + 100 + 5000.00 + 5000.00 + 10.00 + 10.00 + 1800 + 1800 + 10 + 10 + 2 + 900 + 1.1111111111111112 + 900 + 1.1111111111111112 + false + FALSE + 10000000 + div4 + div4 + div4 + div4 + div4 + div4 + div4 + div4 + div4 + div4 + div4 + div4 + div4 + div4 + div4 + div4 + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0xa + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x00 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + true + false + 0x1c61440c0 + false + false + 0x4 + 0x4 + true + false + false + 0 + 0x0002 + false + false + true + false + false + false + false + 0x00000000 + 0x00000000 + false + false + false + 0x00282248 + 0x05 + 0xc61440c0 + 0x00000000 + 0x00000001 + 0x0f38d30b + 0x00061759 + 0x00000 + 0x55134914 + true + true + false + true + false + false + false + false + ROW_BANK_COLUMN + 0x7F + 0x61759551349140f38d30b + false + true + 0x0DB6 + true + true + true + false + false + 0x01E + false + User_Defined + false + true + false + false + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + 8192 + 75 + 75 + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 0x16 + 0x16 + 0x16 + 0x16 + 0x16 + 0x16 + 0x16 + 0x16 + 0x16 + 0x16 + 0x16 + 0x16 + 0x16 + 0x16 + 0x16 + 0x16 + true + true + true + true + true + true + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + LEFT + false + TRUE + TRUE + 100000 + 100000 + 1.0 + 1.0 + 0x07 + 0x07 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + 40 + FALSE + TRUE + 0x00F + 0x00F + 0x1E + 0x1E + 0x0D + 0x0D + 0x09 + 0x09 + 0x2B + 0x2B + 0x90 + 0x90 + 0x0EA + 0x0EA + 0x0D + 0x0D + 0x04 + 0x04 + 0x04 + 0x04 + 0x8 + 0x8 + 0x05 + 0x05 + 0x05 + 0x05 + 0x05 + 0x05 + 0x05 + 0x05 + 0x05 + 0x05 + 0x05 + 0x05 + 0x05 + 0x05 + 0x05 + 0x05 + 0x0F + 0x0F + 0x0F + 0x0F + 0x0F + 0x0F + 0x0F + 0x0F + 0x0F + 0x0F + 0x0F + 0x0F + 0x0F + 0x0F + 0x0F + 0x0F + 0x8 + 0x8 + 0x4 + 0x4 + 0x07 + 0x07 + virtexuplusHBM + + + xcu55n + fsvh2892 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 11 + TRUE + ../../../../XilinxVariumC1100PrbsTester_project.gen/sources_1/ip/HbmDmaBufferIpCore + + . + 2021.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/XilinxVariumC1100/pcie-3x16/rtl/HbmDmaBuffer.vhd b/hardware/XilinxVariumC1100/pcie-3x16/rtl/HbmDmaBuffer.vhd new file mode 100644 index 0000000..e883c28 --- /dev/null +++ b/hardware/XilinxVariumC1100/pcie-3x16/rtl/HbmDmaBuffer.vhd @@ -0,0 +1,834 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: HBM DMA buffer +------------------------------------------------------------------------------- +-- This file is part of 'axi-pcie-core'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'axi-pcie-core', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; + +library axi_pcie_core; + +entity HbmDmaBuffer is + generic ( + TPD_G : time := 1 ns; + DMA_SIZE_G : positive range 1 to 8 := 8; + DMA_AXIS_CONFIG_G : AxiStreamConfigType; + AXIL_BASE_ADDR_G : slv(31 downto 0)); + port ( + -- HBM Interface + hbmRefClk : in sl; + hbmCatTrip : out sl; + -- AXI-Lite Interface (axilClk domain) + axilClk : in sl; + axilRst : in sl; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType; + -- Trigger Event streams (eventClk domain) + eventClk : in sl; + eventTrigMsgCtrl : out AxiStreamCtrlArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_CTRL_INIT_C); + -- AXI Stream Interface (axisClk domain) + axisClk : in sl; + axisRst : in sl; + sAxisMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + sAxisSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + mAxisMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + mAxisSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0)); +end HbmDmaBuffer; + +architecture mapping of HbmDmaBuffer is + + component HbmDmaBufferIpCore + port ( + HBM_REF_CLK_0 : in std_logic; + HBM_REF_CLK_1 : in std_logic; + AXI_00_ACLK : in std_logic; + AXI_00_ARESET_N : in std_logic; + AXI_00_ARADDR : in std_logic_vector(32 downto 0); + AXI_00_ARBURST : in std_logic_vector(1 downto 0); + AXI_00_ARID : in std_logic_vector(5 downto 0); + AXI_00_ARLEN : in std_logic_vector(3 downto 0); + AXI_00_ARSIZE : in std_logic_vector(2 downto 0); + AXI_00_ARVALID : in std_logic; + AXI_00_AWADDR : in std_logic_vector(32 downto 0); + AXI_00_AWBURST : in std_logic_vector(1 downto 0); + AXI_00_AWID : in std_logic_vector(5 downto 0); + AXI_00_AWLEN : in std_logic_vector(3 downto 0); + AXI_00_AWSIZE : in std_logic_vector(2 downto 0); + AXI_00_AWVALID : in std_logic; + AXI_00_RREADY : in std_logic; + AXI_00_BREADY : in std_logic; + AXI_00_WDATA : in std_logic_vector(255 downto 0); + AXI_00_WLAST : in std_logic; + AXI_00_WSTRB : in std_logic_vector(31 downto 0); + AXI_00_WDATA_PARITY : in std_logic_vector(31 downto 0); + AXI_00_WVALID : in std_logic; + AXI_01_ACLK : in std_logic; + AXI_01_ARESET_N : in std_logic; + AXI_01_ARADDR : in std_logic_vector(32 downto 0); + AXI_01_ARBURST : in std_logic_vector(1 downto 0); + AXI_01_ARID : in std_logic_vector(5 downto 0); + AXI_01_ARLEN : in std_logic_vector(3 downto 0); + AXI_01_ARSIZE : in std_logic_vector(2 downto 0); + AXI_01_ARVALID : in std_logic; + AXI_01_AWADDR : in std_logic_vector(32 downto 0); + AXI_01_AWBURST : in std_logic_vector(1 downto 0); + AXI_01_AWID : in std_logic_vector(5 downto 0); + AXI_01_AWLEN : in std_logic_vector(3 downto 0); + AXI_01_AWSIZE : in std_logic_vector(2 downto 0); + AXI_01_AWVALID : in std_logic; + AXI_01_RREADY : in std_logic; + AXI_01_BREADY : in std_logic; + AXI_01_WDATA : in std_logic_vector(255 downto 0); + AXI_01_WLAST : in std_logic; + AXI_01_WSTRB : in std_logic_vector(31 downto 0); + AXI_01_WDATA_PARITY : in std_logic_vector(31 downto 0); + AXI_01_WVALID : in std_logic; + AXI_02_ACLK : in std_logic; + AXI_02_ARESET_N : in std_logic; + AXI_02_ARADDR : in std_logic_vector(32 downto 0); + AXI_02_ARBURST : in std_logic_vector(1 downto 0); + AXI_02_ARID : in std_logic_vector(5 downto 0); + AXI_02_ARLEN : in std_logic_vector(3 downto 0); + AXI_02_ARSIZE : in std_logic_vector(2 downto 0); + AXI_02_ARVALID : in std_logic; + AXI_02_AWADDR : in std_logic_vector(32 downto 0); + AXI_02_AWBURST : in std_logic_vector(1 downto 0); + AXI_02_AWID : in std_logic_vector(5 downto 0); + AXI_02_AWLEN : in std_logic_vector(3 downto 0); + AXI_02_AWSIZE : in std_logic_vector(2 downto 0); + AXI_02_AWVALID : in std_logic; + AXI_02_RREADY : in std_logic; + AXI_02_BREADY : in std_logic; + AXI_02_WDATA : in std_logic_vector(255 downto 0); + AXI_02_WLAST : in std_logic; + AXI_02_WSTRB : in std_logic_vector(31 downto 0); + AXI_02_WDATA_PARITY : in std_logic_vector(31 downto 0); + AXI_02_WVALID : in std_logic; + AXI_03_ACLK : in std_logic; + AXI_03_ARESET_N : in std_logic; + AXI_03_ARADDR : in std_logic_vector(32 downto 0); + AXI_03_ARBURST : in std_logic_vector(1 downto 0); + AXI_03_ARID : in std_logic_vector(5 downto 0); + AXI_03_ARLEN : in std_logic_vector(3 downto 0); + AXI_03_ARSIZE : in std_logic_vector(2 downto 0); + AXI_03_ARVALID : in std_logic; + AXI_03_AWADDR : in std_logic_vector(32 downto 0); + AXI_03_AWBURST : in std_logic_vector(1 downto 0); + AXI_03_AWID : in std_logic_vector(5 downto 0); + AXI_03_AWLEN : in std_logic_vector(3 downto 0); + AXI_03_AWSIZE : in std_logic_vector(2 downto 0); + AXI_03_AWVALID : in std_logic; + AXI_03_RREADY : in std_logic; + AXI_03_BREADY : in std_logic; + AXI_03_WDATA : in std_logic_vector(255 downto 0); + AXI_03_WLAST : in std_logic; + AXI_03_WSTRB : in std_logic_vector(31 downto 0); + AXI_03_WDATA_PARITY : in std_logic_vector(31 downto 0); + AXI_03_WVALID : in std_logic; + AXI_04_ACLK : in std_logic; + AXI_04_ARESET_N : in std_logic; + AXI_04_ARADDR : in std_logic_vector(32 downto 0); + AXI_04_ARBURST : in std_logic_vector(1 downto 0); + AXI_04_ARID : in std_logic_vector(5 downto 0); + AXI_04_ARLEN : in std_logic_vector(3 downto 0); + AXI_04_ARSIZE : in std_logic_vector(2 downto 0); + AXI_04_ARVALID : in std_logic; + AXI_04_AWADDR : in std_logic_vector(32 downto 0); + AXI_04_AWBURST : in std_logic_vector(1 downto 0); + AXI_04_AWID : in std_logic_vector(5 downto 0); + AXI_04_AWLEN : in std_logic_vector(3 downto 0); + AXI_04_AWSIZE : in std_logic_vector(2 downto 0); + AXI_04_AWVALID : in std_logic; + AXI_04_RREADY : in std_logic; + AXI_04_BREADY : in std_logic; + AXI_04_WDATA : in std_logic_vector(255 downto 0); + AXI_04_WLAST : in std_logic; + AXI_04_WSTRB : in std_logic_vector(31 downto 0); + AXI_04_WDATA_PARITY : in std_logic_vector(31 downto 0); + AXI_04_WVALID : in std_logic; + AXI_05_ACLK : in std_logic; + AXI_05_ARESET_N : in std_logic; + AXI_05_ARADDR : in std_logic_vector(32 downto 0); + AXI_05_ARBURST : in std_logic_vector(1 downto 0); + AXI_05_ARID : in std_logic_vector(5 downto 0); + AXI_05_ARLEN : in std_logic_vector(3 downto 0); + AXI_05_ARSIZE : in std_logic_vector(2 downto 0); + AXI_05_ARVALID : in std_logic; + AXI_05_AWADDR : in std_logic_vector(32 downto 0); + AXI_05_AWBURST : in std_logic_vector(1 downto 0); + AXI_05_AWID : in std_logic_vector(5 downto 0); + AXI_05_AWLEN : in std_logic_vector(3 downto 0); + AXI_05_AWSIZE : in std_logic_vector(2 downto 0); + AXI_05_AWVALID : in std_logic; + AXI_05_RREADY : in std_logic; + AXI_05_BREADY : in std_logic; + AXI_05_WDATA : in std_logic_vector(255 downto 0); + AXI_05_WLAST : in std_logic; + AXI_05_WSTRB : in std_logic_vector(31 downto 0); + AXI_05_WDATA_PARITY : in std_logic_vector(31 downto 0); + AXI_05_WVALID : in std_logic; + AXI_06_ACLK : in std_logic; + AXI_06_ARESET_N : in std_logic; + AXI_06_ARADDR : in std_logic_vector(32 downto 0); + AXI_06_ARBURST : in std_logic_vector(1 downto 0); + AXI_06_ARID : in std_logic_vector(5 downto 0); + AXI_06_ARLEN : in std_logic_vector(3 downto 0); + AXI_06_ARSIZE : in std_logic_vector(2 downto 0); + AXI_06_ARVALID : in std_logic; + AXI_06_AWADDR : in std_logic_vector(32 downto 0); + AXI_06_AWBURST : in std_logic_vector(1 downto 0); + AXI_06_AWID : in std_logic_vector(5 downto 0); + AXI_06_AWLEN : in std_logic_vector(3 downto 0); + AXI_06_AWSIZE : in std_logic_vector(2 downto 0); + AXI_06_AWVALID : in std_logic; + AXI_06_RREADY : in std_logic; + AXI_06_BREADY : in std_logic; + AXI_06_WDATA : in std_logic_vector(255 downto 0); + AXI_06_WLAST : in std_logic; + AXI_06_WSTRB : in std_logic_vector(31 downto 0); + AXI_06_WDATA_PARITY : in std_logic_vector(31 downto 0); + AXI_06_WVALID : in std_logic; + AXI_07_ACLK : in std_logic; + AXI_07_ARESET_N : in std_logic; + AXI_07_ARADDR : in std_logic_vector(32 downto 0); + AXI_07_ARBURST : in std_logic_vector(1 downto 0); + AXI_07_ARID : in std_logic_vector(5 downto 0); + AXI_07_ARLEN : in std_logic_vector(3 downto 0); + AXI_07_ARSIZE : in std_logic_vector(2 downto 0); + AXI_07_ARVALID : in std_logic; + AXI_07_AWADDR : in std_logic_vector(32 downto 0); + AXI_07_AWBURST : in std_logic_vector(1 downto 0); + AXI_07_AWID : in std_logic_vector(5 downto 0); + AXI_07_AWLEN : in std_logic_vector(3 downto 0); + AXI_07_AWSIZE : in std_logic_vector(2 downto 0); + AXI_07_AWVALID : in std_logic; + AXI_07_RREADY : in std_logic; + AXI_07_BREADY : in std_logic; + AXI_07_WDATA : in std_logic_vector(255 downto 0); + AXI_07_WLAST : in std_logic; + AXI_07_WSTRB : in std_logic_vector(31 downto 0); + AXI_07_WDATA_PARITY : in std_logic_vector(31 downto 0); + AXI_07_WVALID : in std_logic; + APB_0_PCLK : in std_logic; + APB_0_PRESET_N : in std_logic; + APB_1_PCLK : in std_logic; + APB_1_PRESET_N : in std_logic; + AXI_00_ARREADY : out std_logic; + AXI_00_AWREADY : out std_logic; + AXI_00_RDATA_PARITY : out std_logic_vector(31 downto 0); + AXI_00_RDATA : out std_logic_vector(255 downto 0); + AXI_00_RID : out std_logic_vector(5 downto 0); + AXI_00_RLAST : out std_logic; + AXI_00_RRESP : out std_logic_vector(1 downto 0); + AXI_00_RVALID : out std_logic; + AXI_00_WREADY : out std_logic; + AXI_00_BID : out std_logic_vector(5 downto 0); + AXI_00_BRESP : out std_logic_vector(1 downto 0); + AXI_00_BVALID : out std_logic; + AXI_01_ARREADY : out std_logic; + AXI_01_AWREADY : out std_logic; + AXI_01_RDATA_PARITY : out std_logic_vector(31 downto 0); + AXI_01_RDATA : out std_logic_vector(255 downto 0); + AXI_01_RID : out std_logic_vector(5 downto 0); + AXI_01_RLAST : out std_logic; + AXI_01_RRESP : out std_logic_vector(1 downto 0); + AXI_01_RVALID : out std_logic; + AXI_01_WREADY : out std_logic; + AXI_01_BID : out std_logic_vector(5 downto 0); + AXI_01_BRESP : out std_logic_vector(1 downto 0); + AXI_01_BVALID : out std_logic; + AXI_02_ARREADY : out std_logic; + AXI_02_AWREADY : out std_logic; + AXI_02_RDATA_PARITY : out std_logic_vector(31 downto 0); + AXI_02_RDATA : out std_logic_vector(255 downto 0); + AXI_02_RID : out std_logic_vector(5 downto 0); + AXI_02_RLAST : out std_logic; + AXI_02_RRESP : out std_logic_vector(1 downto 0); + AXI_02_RVALID : out std_logic; + AXI_02_WREADY : out std_logic; + AXI_02_BID : out std_logic_vector(5 downto 0); + AXI_02_BRESP : out std_logic_vector(1 downto 0); + AXI_02_BVALID : out std_logic; + AXI_03_ARREADY : out std_logic; + AXI_03_AWREADY : out std_logic; + AXI_03_RDATA_PARITY : out std_logic_vector(31 downto 0); + AXI_03_RDATA : out std_logic_vector(255 downto 0); + AXI_03_RID : out std_logic_vector(5 downto 0); + AXI_03_RLAST : out std_logic; + AXI_03_RRESP : out std_logic_vector(1 downto 0); + AXI_03_RVALID : out std_logic; + AXI_03_WREADY : out std_logic; + AXI_03_BID : out std_logic_vector(5 downto 0); + AXI_03_BRESP : out std_logic_vector(1 downto 0); + AXI_03_BVALID : out std_logic; + AXI_04_ARREADY : out std_logic; + AXI_04_AWREADY : out std_logic; + AXI_04_RDATA_PARITY : out std_logic_vector(31 downto 0); + AXI_04_RDATA : out std_logic_vector(255 downto 0); + AXI_04_RID : out std_logic_vector(5 downto 0); + AXI_04_RLAST : out std_logic; + AXI_04_RRESP : out std_logic_vector(1 downto 0); + AXI_04_RVALID : out std_logic; + AXI_04_WREADY : out std_logic; + AXI_04_BID : out std_logic_vector(5 downto 0); + AXI_04_BRESP : out std_logic_vector(1 downto 0); + AXI_04_BVALID : out std_logic; + AXI_05_ARREADY : out std_logic; + AXI_05_AWREADY : out std_logic; + AXI_05_RDATA_PARITY : out std_logic_vector(31 downto 0); + AXI_05_RDATA : out std_logic_vector(255 downto 0); + AXI_05_RID : out std_logic_vector(5 downto 0); + AXI_05_RLAST : out std_logic; + AXI_05_RRESP : out std_logic_vector(1 downto 0); + AXI_05_RVALID : out std_logic; + AXI_05_WREADY : out std_logic; + AXI_05_BID : out std_logic_vector(5 downto 0); + AXI_05_BRESP : out std_logic_vector(1 downto 0); + AXI_05_BVALID : out std_logic; + AXI_06_ARREADY : out std_logic; + AXI_06_AWREADY : out std_logic; + AXI_06_RDATA_PARITY : out std_logic_vector(31 downto 0); + AXI_06_RDATA : out std_logic_vector(255 downto 0); + AXI_06_RID : out std_logic_vector(5 downto 0); + AXI_06_RLAST : out std_logic; + AXI_06_RRESP : out std_logic_vector(1 downto 0); + AXI_06_RVALID : out std_logic; + AXI_06_WREADY : out std_logic; + AXI_06_BID : out std_logic_vector(5 downto 0); + AXI_06_BRESP : out std_logic_vector(1 downto 0); + AXI_06_BVALID : out std_logic; + AXI_07_ARREADY : out std_logic; + AXI_07_AWREADY : out std_logic; + AXI_07_RDATA_PARITY : out std_logic_vector(31 downto 0); + AXI_07_RDATA : out std_logic_vector(255 downto 0); + AXI_07_RID : out std_logic_vector(5 downto 0); + AXI_07_RLAST : out std_logic; + AXI_07_RRESP : out std_logic_vector(1 downto 0); + AXI_07_RVALID : out std_logic; + AXI_07_WREADY : out std_logic; + AXI_07_BID : out std_logic_vector(5 downto 0); + AXI_07_BRESP : out std_logic_vector(1 downto 0); + AXI_07_BVALID : out std_logic; + apb_complete_0 : out std_logic; + apb_complete_1 : out std_logic; + DRAM_0_STAT_CATTRIP : out std_logic; + DRAM_0_STAT_TEMP : out std_logic_vector(6 downto 0); + DRAM_1_STAT_CATTRIP : out std_logic; + DRAM_1_STAT_TEMP : out std_logic_vector(6 downto 0) + ); + end component; + + -- HBM MEM AXI Configuration + constant MEM_AXI_CONFIG_C : AxiConfigType := ( + ADDR_WIDTH_C => 33, -- 8GB HBM + DATA_BYTES_C => 32, -- 256-bit data interface + ID_BITS_C => 6, -- Up to 64 IDS + LEN_BITS_C => 4); -- 4-bit awlen/arlen interface + + constant AXI_BUFFER_WIDTH_C : positive := MEM_AXI_CONFIG_C.ADDR_WIDTH_C-3; -- 8 GB HBM shared between 8 DMA lanes + constant AXI_BASE_ADDR_C : Slv64Array(7 downto 0) := ( + 0 => x"0000_0000_0000_0000", + 1 => x"0000_0000_4000_0000", -- 1GB partitions + 2 => x"0000_0000_8000_0000", + 3 => x"0000_0000_C000_0000", + 4 => x"0000_0001_0000_0000", + 5 => x"0000_0001_4000_0000", + 6 => x"0000_0001_8000_0000", + 7 => x"0000_0001_C000_0000"); + + constant DMA_AXI_CONFIG_C : AxiConfigType := ( + ADDR_WIDTH_C => 40, -- Match 40-bit address for axi_pcie_core.AxiPcieResizer + DATA_BYTES_C => DMA_AXIS_CONFIG_G.TDATA_BYTES_C, -- Matches the AXIS stream because you ***CANNOT*** resize an interleaved AXI stream + ID_BITS_C => MEM_AXI_CONFIG_C.ID_BITS_C, + LEN_BITS_C => MEM_AXI_CONFIG_C.LEN_BITS_C); + + constant INT_DMA_AXI_CONFIG_C : AxiConfigType := ( + ADDR_WIDTH_C => 40, -- Match 40-bit address for axi_pcie_core.AxiPcieResizer + DATA_BYTES_C => MEM_AXI_CONFIG_C.DATA_BYTES_C, -- Actual memory interface width + ID_BITS_C => MEM_AXI_CONFIG_C.ID_BITS_C, + LEN_BITS_C => MEM_AXI_CONFIG_C.LEN_BITS_C); + + constant AXIL_XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(DMA_SIZE_G-1 downto 0) := genAxiLiteConfig(DMA_SIZE_G, AXIL_BASE_ADDR_G, 12, 8); + + signal axilWriteMasters : AxiLiteWriteMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_LITE_WRITE_MASTER_INIT_C); + signal axilWriteSlaves : AxiLiteWriteSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); + signal axilReadMasters : AxiLiteReadMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_LITE_READ_MASTER_INIT_C); + signal axilReadSlaves : AxiLiteReadSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C); + + signal memWriteMasters : AxiWriteMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_WRITE_MASTER_INIT_C); + signal memWriteSlaves : AxiWriteSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_WRITE_SLAVE_INIT_C); + signal memReadMasters : AxiReadMasterArray(DMA_SIZE_G-1 downto 0) := (others => AXI_READ_MASTER_INIT_C); + signal memReadSlaves : AxiReadSlaveArray(DMA_SIZE_G-1 downto 0) := (others => AXI_READ_SLAVE_INIT_C); + + signal axiWriteMasters : AxiWriteMasterArray(7 downto 0) := (others => AXI_WRITE_MASTER_INIT_C); + signal axiWriteSlaves : AxiWriteSlaveArray(7 downto 0) := (others => AXI_WRITE_SLAVE_INIT_C); + signal axiReadMasters : AxiReadMasterArray(7 downto 0) := (others => AXI_READ_MASTER_INIT_C); + signal axiReadSlaves : AxiReadSlaveArray(7 downto 0) := (others => AXI_READ_SLAVE_INIT_C); + + signal sAxisCtrl : AxiStreamCtrlArray(DMA_SIZE_G-1 downto 0) := (others => AXI_STREAM_CTRL_INIT_C); + + signal axisReset : slv(7 downto 0); + signal axisRstL : slv(7 downto 0); + signal hbmCatTripVec : slv(1 downto 0); + signal apbDoneVec : slv(1 downto 0); + signal apbDone : sl; + signal apbDoneSync : sl; + signal apbRstL : sl; + signal axiReady : slv(7 downto 0); + signal wdataParity : Slv32Array(7 downto 0) := (others => (others => '0')); + +begin + + -- Help with timing + U_axisReset : entity surf.RstPipelineVector + generic map ( + TPD_G => TPD_G, + WIDTH_G => 8, + INV_RST_G => false) + port map ( + clk => axisClk, + rstIn => (others => axisRst), + rstOut => axisReset); + + -- Help with timing + U_axisRstL : entity surf.RstPipelineVector + generic map ( + TPD_G => TPD_G, + WIDTH_G => 8, + INV_RST_G => true) -- invert reset + port map ( + clk => axisClk, + rstIn => (others => axisRst), -- active HIGH + rstOut => axisRstL); -- active LOW + + -------------------- + -- AXI-Lite Crossbar + -------------------- + U_XBAR : entity surf.AxiLiteCrossbar + generic map ( + TPD_G => TPD_G, + NUM_SLAVE_SLOTS_G => 1, + NUM_MASTER_SLOTS_G => DMA_SIZE_G, + MASTERS_CONFIG_G => AXIL_XBAR_CONFIG_C) + port map ( + axiClk => axilClk, + axiClkRst => axilRst, + sAxiWriteMasters(0) => axilWriteMaster, + sAxiWriteSlaves(0) => axilWriteSlave, + sAxiReadMasters(0) => axilReadMaster, + sAxiReadSlaves(0) => axilReadSlave, + mAxiWriteMasters => axilWriteMasters, + mAxiWriteSlaves => axilWriteSlaves, + mAxiReadMasters => axilReadMasters, + mAxiReadSlaves => axilReadSlaves); + + GEN_FIFO : for i in DMA_SIZE_G-1 downto 0 generate + + U_pause : entity surf.Synchronizer + generic map ( + TPD_G => TPD_G) + port map ( + clk => eventClk, + dataIn => sAxisCtrl(i).pause, + dataOut => eventTrigMsgCtrl(i).pause); + + U_AxiFifo : entity surf.AxiStreamDmaV2Fifo + generic map ( + TPD_G => TPD_G, + -- FIFO Configuration + BUFF_FRAME_WIDTH_G => AXI_BUFFER_WIDTH_C-12, -- Optimized to fix into 1 URAM (12-bit address) for free list + AXI_BUFFER_WIDTH_G => AXI_BUFFER_WIDTH_C, + SYNTH_MODE_G => "xpm", + MEMORY_TYPE_G => "ultra", + -- AXI Stream Configurations + AXIS_CONFIG_G => DMA_AXIS_CONFIG_G, + -- AXI4 Configurations + AXI_BASE_ADDR_G => AXI_BASE_ADDR_C(i), + AXI_CONFIG_G => DMA_AXI_CONFIG_C, + BURST_BYTES_G => 256) -- Match the HBM AXI switch's native max block transfer + port map ( + -- AXI4 Interface (axiClk domain) + axiClk => axisClk, + axiRst => axisReset(i), + axiReady => axiReady(i), + axiReadMaster => memReadMasters(i), + axiReadSlave => memReadSlaves(i), + axiWriteMaster => memWriteMasters(i), + axiWriteSlave => memWriteSlaves(i), + -- AXI Stream Interface (axiClk domain) + sAxisMaster => sAxisMasters(i), + sAxisSlave => sAxisSlaves(i), + sAxisCtrl => sAxisCtrl(i), + mAxisMaster => mAxisMasters(i), + mAxisSlave => mAxisSlaves(i), + -- Optional: AXI-Lite Interface (axilClk domain) + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMasters(i), + axilReadSlave => axilReadSlaves(i), + axilWriteMaster => axilWriteMasters(i), + axilWriteSlave => axilWriteSlaves(i)); + + U_Resizer : entity axi_pcie_core.AxiPcieResizer + generic map( + TPD_G => TPD_G, + AXI_DMA_CONFIG_G => DMA_AXI_CONFIG_C, + AXI_PCIE_CONFIG_G => INT_DMA_AXI_CONFIG_C) + port map( + -- Clock and reset + axiClk => axisClk, + axiRst => axisReset(i), + -- Slave Port + sAxiReadMaster => memReadMasters(i), + sAxiReadSlave => memReadSlaves(i), + sAxiWriteMaster => memWriteMasters(i), + sAxiWriteSlave => memWriteSlaves(i), + -- Master Port + mAxiReadMaster => axiReadMasters(i), + mAxiReadSlave => axiReadSlaves(i), + mAxiWriteMaster => axiWriteMasters(i), + mAxiWriteSlave => axiWriteSlaves(i)); + + GEN_VEC : for j in MEM_AXI_CONFIG_C.DATA_BYTES_C-1 downto 0 generate + wdataParity(i)(j) <= oddParity(axiWriteMasters(i).wdata(8*j+7 downto 8*j)); + end generate; + + end generate; + + U_HBM : HbmDmaBufferIpCore + port map ( + -- Reference Clocks + HBM_REF_CLK_0 => hbmRefClk, + HBM_REF_CLK_1 => hbmRefClk, + -- AXI_00 Interface + AXI_00_ACLK => axisClk, + AXI_00_ARESET_N => axisRstL(0), + AXI_00_ARADDR => axiReadMasters(0).araddr(32 downto 0), + AXI_00_ARBURST => axiReadMasters(0).arburst, + AXI_00_ARID => toSlv(0, 6), + AXI_00_ARLEN => axiReadMasters(0).arlen(3 downto 0), -- 4-bits = AXI3 + AXI_00_ARSIZE => axiReadMasters(0).arsize, + AXI_00_ARVALID => axiReadMasters(0).arvalid, + AXI_00_AWADDR => axiWriteMasters(0).awaddr(32 downto 0), + AXI_00_AWBURST => axiWriteMasters(0).awburst, + AXI_00_AWID => toSlv(0, 6), + AXI_00_AWLEN => axiWriteMasters(0).awlen(3 downto 0), -- 4-bits = AXI3 + AXI_00_AWSIZE => axiWriteMasters(0).awsize, + AXI_00_AWVALID => axiWriteMasters(0).awvalid, + AXI_00_RREADY => axiReadMasters(0).rready, + AXI_00_BREADY => axiWriteMasters(0).bready, + AXI_00_WDATA => axiWriteMasters(0).wdata(255 downto 0), + AXI_00_WLAST => axiWriteMasters(0).wlast, + AXI_00_WSTRB => axiWriteMasters(0).wstrb(31 downto 0), + AXI_00_WDATA_PARITY => wdataParity(0), + AXI_00_WVALID => axiWriteMasters(0).wvalid, + AXI_00_ARREADY => axiReadSlaves(0).arready, + AXI_00_AWREADY => axiWriteSlaves(0).awready, + AXI_00_RDATA_PARITY => open, + AXI_00_RDATA => axiReadSlaves(0).rdata(255 downto 0), + AXI_00_RID => open, + AXI_00_RLAST => axiReadSlaves(0).rlast, + AXI_00_RRESP => axiReadSlaves(0).rresp, + AXI_00_RVALID => axiReadSlaves(0).rvalid, + AXI_00_WREADY => axiWriteSlaves(0).wready, + AXI_00_BID => open, + AXI_00_BRESP => axiWriteSlaves(0).bresp, + AXI_00_BVALID => axiWriteSlaves(0).bvalid, + -- AXI_01 Interface + AXI_01_ACLK => axisClk, + AXI_01_ARESET_N => axisRstL(1), + AXI_01_ARADDR => axiReadMasters(1).araddr(32 downto 0), + AXI_01_ARBURST => axiReadMasters(1).arburst, + AXI_01_ARID => toSlv(1, 6), + AXI_01_ARLEN => axiReadMasters(1).arlen(3 downto 0), -- 4-bits = AXI3 + AXI_01_ARSIZE => axiReadMasters(1).arsize, + AXI_01_ARVALID => axiReadMasters(1).arvalid, + AXI_01_AWADDR => axiWriteMasters(1).awaddr(32 downto 0), + AXI_01_AWBURST => axiWriteMasters(1).awburst, + AXI_01_AWID => toSlv(1, 6), + AXI_01_AWLEN => axiWriteMasters(1).awlen(3 downto 0), -- 4-bits = AXI3 + AXI_01_AWSIZE => axiWriteMasters(1).awsize, + AXI_01_AWVALID => axiWriteMasters(1).awvalid, + AXI_01_RREADY => axiReadMasters(1).rready, + AXI_01_BREADY => axiWriteMasters(1).bready, + AXI_01_WDATA => axiWriteMasters(1).wdata(255 downto 0), + AXI_01_WLAST => axiWriteMasters(1).wlast, + AXI_01_WSTRB => axiWriteMasters(1).wstrb(31 downto 0), + AXI_01_WDATA_PARITY => wdataParity(1), + AXI_01_WVALID => axiWriteMasters(1).wvalid, + AXI_01_ARREADY => axiReadSlaves(1).arready, + AXI_01_AWREADY => axiWriteSlaves(1).awready, + AXI_01_RDATA_PARITY => open, + AXI_01_RDATA => axiReadSlaves(1).rdata(255 downto 0), + AXI_01_RID => open, + AXI_01_RLAST => axiReadSlaves(1).rlast, + AXI_01_RRESP => axiReadSlaves(1).rresp, + AXI_01_RVALID => axiReadSlaves(1).rvalid, + AXI_01_WREADY => axiWriteSlaves(1).wready, + AXI_01_BID => open, + AXI_01_BRESP => axiWriteSlaves(1).bresp, + AXI_01_BVALID => axiWriteSlaves(1).bvalid, + -- AXI_02 Interface + AXI_02_ACLK => axisClk, + AXI_02_ARESET_N => axisRstL(2), + AXI_02_ARADDR => axiReadMasters(2).araddr(32 downto 0), + AXI_02_ARBURST => axiReadMasters(2).arburst, + AXI_02_ARID => toSlv(2, 6), + AXI_02_ARLEN => axiReadMasters(2).arlen(3 downto 0), -- 4-bits = AXI3 + AXI_02_ARSIZE => axiReadMasters(2).arsize, + AXI_02_ARVALID => axiReadMasters(2).arvalid, + AXI_02_AWADDR => axiWriteMasters(2).awaddr(32 downto 0), + AXI_02_AWBURST => axiWriteMasters(2).awburst, + AXI_02_AWID => toSlv(2, 6), + AXI_02_AWLEN => axiWriteMasters(2).awlen(3 downto 0), -- 4-bits = AXI3 + AXI_02_AWSIZE => axiWriteMasters(2).awsize, + AXI_02_AWVALID => axiWriteMasters(2).awvalid, + AXI_02_RREADY => axiReadMasters(2).rready, + AXI_02_BREADY => axiWriteMasters(2).bready, + AXI_02_WDATA => axiWriteMasters(2).wdata(255 downto 0), + AXI_02_WLAST => axiWriteMasters(2).wlast, + AXI_02_WSTRB => axiWriteMasters(2).wstrb(31 downto 0), + AXI_02_WDATA_PARITY => wdataParity(2), + AXI_02_WVALID => axiWriteMasters(2).wvalid, + AXI_02_ARREADY => axiReadSlaves(2).arready, + AXI_02_AWREADY => axiWriteSlaves(2).awready, + AXI_02_RDATA_PARITY => open, + AXI_02_RDATA => axiReadSlaves(2).rdata(255 downto 0), + AXI_02_RID => open, + AXI_02_RLAST => axiReadSlaves(2).rlast, + AXI_02_RRESP => axiReadSlaves(2).rresp, + AXI_02_RVALID => axiReadSlaves(2).rvalid, + AXI_02_WREADY => axiWriteSlaves(2).wready, + AXI_02_BID => open, + AXI_02_BRESP => axiWriteSlaves(2).bresp, + AXI_02_BVALID => axiWriteSlaves(2).bvalid, + -- AXI_03 Interface + AXI_03_ACLK => axisClk, + AXI_03_ARESET_N => axisRstL(3), + AXI_03_ARADDR => axiReadMasters(3).araddr(32 downto 0), + AXI_03_ARBURST => axiReadMasters(3).arburst, + AXI_03_ARID => toSlv(3, 6), + AXI_03_ARLEN => axiReadMasters(3).arlen(3 downto 0), -- 4-bits = AXI3 + AXI_03_ARSIZE => axiReadMasters(3).arsize, + AXI_03_ARVALID => axiReadMasters(3).arvalid, + AXI_03_AWADDR => axiWriteMasters(3).awaddr(32 downto 0), + AXI_03_AWBURST => axiWriteMasters(3).awburst, + AXI_03_AWID => toSlv(3, 6), + AXI_03_AWLEN => axiWriteMasters(3).awlen(3 downto 0), -- 4-bits = AXI3 + AXI_03_AWSIZE => axiWriteMasters(3).awsize, + AXI_03_AWVALID => axiWriteMasters(3).awvalid, + AXI_03_RREADY => axiReadMasters(3).rready, + AXI_03_BREADY => axiWriteMasters(3).bready, + AXI_03_WDATA => axiWriteMasters(3).wdata(255 downto 0), + AXI_03_WLAST => axiWriteMasters(3).wlast, + AXI_03_WSTRB => axiWriteMasters(3).wstrb(31 downto 0), + AXI_03_WDATA_PARITY => wdataParity(3), + AXI_03_WVALID => axiWriteMasters(3).wvalid, + AXI_03_ARREADY => axiReadSlaves(3).arready, + AXI_03_AWREADY => axiWriteSlaves(3).awready, + AXI_03_RDATA_PARITY => open, + AXI_03_RDATA => axiReadSlaves(3).rdata(255 downto 0), + AXI_03_RID => open, + AXI_03_RLAST => axiReadSlaves(3).rlast, + AXI_03_RRESP => axiReadSlaves(3).rresp, + AXI_03_RVALID => axiReadSlaves(3).rvalid, + AXI_03_WREADY => axiWriteSlaves(3).wready, + AXI_03_BID => open, + AXI_03_BRESP => axiWriteSlaves(3).bresp, + AXI_03_BVALID => axiWriteSlaves(3).bvalid, + -- AXI_04 Interface + AXI_04_ACLK => axisClk, + AXI_04_ARESET_N => axisRstL(4), + AXI_04_ARADDR => axiReadMasters(4).araddr(32 downto 0), + AXI_04_ARBURST => axiReadMasters(4).arburst, + AXI_04_ARID => toSlv(4, 6), + AXI_04_ARLEN => axiReadMasters(4).arlen(3 downto 0), -- 4-bits = AXI3 + AXI_04_ARSIZE => axiReadMasters(4).arsize, + AXI_04_ARVALID => axiReadMasters(4).arvalid, + AXI_04_AWADDR => axiWriteMasters(4).awaddr(32 downto 0), + AXI_04_AWBURST => axiWriteMasters(4).awburst, + AXI_04_AWID => toSlv(4, 6), + AXI_04_AWLEN => axiWriteMasters(4).awlen(3 downto 0), -- 4-bits = AXI3 + AXI_04_AWSIZE => axiWriteMasters(4).awsize, + AXI_04_AWVALID => axiWriteMasters(4).awvalid, + AXI_04_RREADY => axiReadMasters(4).rready, + AXI_04_BREADY => axiWriteMasters(4).bready, + AXI_04_WDATA => axiWriteMasters(4).wdata(255 downto 0), + AXI_04_WLAST => axiWriteMasters(4).wlast, + AXI_04_WSTRB => axiWriteMasters(4).wstrb(31 downto 0), + AXI_04_WDATA_PARITY => wdataParity(4), + AXI_04_WVALID => axiWriteMasters(4).wvalid, + AXI_04_ARREADY => axiReadSlaves(4).arready, + AXI_04_AWREADY => axiWriteSlaves(4).awready, + AXI_04_RDATA_PARITY => open, + AXI_04_RDATA => axiReadSlaves(4).rdata(255 downto 0), + AXI_04_RID => open, + AXI_04_RLAST => axiReadSlaves(4).rlast, + AXI_04_RRESP => axiReadSlaves(4).rresp, + AXI_04_RVALID => axiReadSlaves(4).rvalid, + AXI_04_WREADY => axiWriteSlaves(4).wready, + AXI_04_BID => open, + AXI_04_BRESP => axiWriteSlaves(4).bresp, + AXI_04_BVALID => axiWriteSlaves(4).bvalid, + -- AXI_05 Interface + AXI_05_ACLK => axisClk, + AXI_05_ARESET_N => axisRstL(5), + AXI_05_ARADDR => axiReadMasters(5).araddr(32 downto 0), + AXI_05_ARBURST => axiReadMasters(5).arburst, + AXI_05_ARID => toSlv(5, 6), + AXI_05_ARLEN => axiReadMasters(5).arlen(3 downto 0), -- 4-bits = AXI3 + AXI_05_ARSIZE => axiReadMasters(5).arsize, + AXI_05_ARVALID => axiReadMasters(5).arvalid, + AXI_05_AWADDR => axiWriteMasters(5).awaddr(32 downto 0), + AXI_05_AWBURST => axiWriteMasters(5).awburst, + AXI_05_AWID => toSlv(5, 6), + AXI_05_AWLEN => axiWriteMasters(5).awlen(3 downto 0), -- 4-bits = AXI3 + AXI_05_AWSIZE => axiWriteMasters(5).awsize, + AXI_05_AWVALID => axiWriteMasters(5).awvalid, + AXI_05_RREADY => axiReadMasters(5).rready, + AXI_05_BREADY => axiWriteMasters(5).bready, + AXI_05_WDATA => axiWriteMasters(5).wdata(255 downto 0), + AXI_05_WLAST => axiWriteMasters(5).wlast, + AXI_05_WSTRB => axiWriteMasters(5).wstrb(31 downto 0), + AXI_05_WDATA_PARITY => wdataParity(5), + AXI_05_WVALID => axiWriteMasters(5).wvalid, + AXI_05_ARREADY => axiReadSlaves(5).arready, + AXI_05_AWREADY => axiWriteSlaves(5).awready, + AXI_05_RDATA_PARITY => open, + AXI_05_RDATA => axiReadSlaves(5).rdata(255 downto 0), + AXI_05_RID => open, + AXI_05_RLAST => axiReadSlaves(5).rlast, + AXI_05_RRESP => axiReadSlaves(5).rresp, + AXI_05_RVALID => axiReadSlaves(5).rvalid, + AXI_05_WREADY => axiWriteSlaves(5).wready, + AXI_05_BID => open, + AXI_05_BRESP => axiWriteSlaves(5).bresp, + AXI_05_BVALID => axiWriteSlaves(5).bvalid, + -- AXI_06 Interface + AXI_06_ACLK => axisClk, + AXI_06_ARESET_N => axisRstL(6), + AXI_06_ARADDR => axiReadMasters(6).araddr(32 downto 0), + AXI_06_ARBURST => axiReadMasters(6).arburst, + AXI_06_ARID => toSlv(6, 6), + AXI_06_ARLEN => axiReadMasters(6).arlen(3 downto 0), -- 4-bits = AXI3 + AXI_06_ARSIZE => axiReadMasters(6).arsize, + AXI_06_ARVALID => axiReadMasters(6).arvalid, + AXI_06_AWADDR => axiWriteMasters(6).awaddr(32 downto 0), + AXI_06_AWBURST => axiWriteMasters(6).awburst, + AXI_06_AWID => toSlv(6, 6), + AXI_06_AWLEN => axiWriteMasters(6).awlen(3 downto 0), -- 4-bits = AXI3 + AXI_06_AWSIZE => axiWriteMasters(6).awsize, + AXI_06_AWVALID => axiWriteMasters(6).awvalid, + AXI_06_RREADY => axiReadMasters(6).rready, + AXI_06_BREADY => axiWriteMasters(6).bready, + AXI_06_WDATA => axiWriteMasters(6).wdata(255 downto 0), + AXI_06_WLAST => axiWriteMasters(6).wlast, + AXI_06_WSTRB => axiWriteMasters(6).wstrb(31 downto 0), + AXI_06_WDATA_PARITY => wdataParity(6), + AXI_06_WVALID => axiWriteMasters(6).wvalid, + AXI_06_ARREADY => axiReadSlaves(6).arready, + AXI_06_AWREADY => axiWriteSlaves(6).awready, + AXI_06_RDATA_PARITY => open, + AXI_06_RDATA => axiReadSlaves(6).rdata(255 downto 0), + AXI_06_RID => open, + AXI_06_RLAST => axiReadSlaves(6).rlast, + AXI_06_RRESP => axiReadSlaves(6).rresp, + AXI_06_RVALID => axiReadSlaves(6).rvalid, + AXI_06_WREADY => axiWriteSlaves(6).wready, + AXI_06_BID => open, + AXI_06_BRESP => axiWriteSlaves(6).bresp, + AXI_06_BVALID => axiWriteSlaves(6).bvalid, + -- AXI_07 Interface + AXI_07_ACLK => axisClk, + AXI_07_ARESET_N => axisRstL(7), + AXI_07_ARADDR => axiReadMasters(7).araddr(32 downto 0), + AXI_07_ARBURST => axiReadMasters(7).arburst, + AXI_07_ARID => toSlv(7, 6), + AXI_07_ARLEN => axiReadMasters(7).arlen(3 downto 0), -- 4-bits = AXI3 + AXI_07_ARSIZE => axiReadMasters(7).arsize, + AXI_07_ARVALID => axiReadMasters(7).arvalid, + AXI_07_AWADDR => axiWriteMasters(7).awaddr(32 downto 0), + AXI_07_AWBURST => axiWriteMasters(7).awburst, + AXI_07_AWID => toSlv(7, 6), + AXI_07_AWLEN => axiWriteMasters(7).awlen(3 downto 0), -- 4-bits = AXI3 + AXI_07_AWSIZE => axiWriteMasters(7).awsize, + AXI_07_AWVALID => axiWriteMasters(7).awvalid, + AXI_07_RREADY => axiReadMasters(7).rready, + AXI_07_BREADY => axiWriteMasters(7).bready, + AXI_07_WDATA => axiWriteMasters(7).wdata(255 downto 0), + AXI_07_WLAST => axiWriteMasters(7).wlast, + AXI_07_WSTRB => axiWriteMasters(7).wstrb(31 downto 0), + AXI_07_WDATA_PARITY => wdataParity(7), + AXI_07_WVALID => axiWriteMasters(7).wvalid, + AXI_07_ARREADY => axiReadSlaves(7).arready, + AXI_07_AWREADY => axiWriteSlaves(7).awready, + AXI_07_RDATA_PARITY => open, + AXI_07_RDATA => axiReadSlaves(7).rdata(255 downto 0), + AXI_07_RID => open, + AXI_07_RLAST => axiReadSlaves(7).rlast, + AXI_07_RRESP => axiReadSlaves(7).rresp, + AXI_07_RVALID => axiReadSlaves(7).rvalid, + AXI_07_WREADY => axiWriteSlaves(7).wready, + AXI_07_BID => open, + AXI_07_BRESP => axiWriteSlaves(7).bresp, + AXI_07_BVALID => axiWriteSlaves(7).bvalid, + -- APB Interface + APB_0_PCLK => hbmRefClk, + APB_1_PCLK => hbmRefClk, + APB_0_PRESET_N => apbRstL, + APB_1_PRESET_N => apbRstL, + apb_complete_0 => apbDoneVec(0), + apb_complete_1 => apbDoneVec(1), + DRAM_0_STAT_CATTRIP => hbmCatTripVec(0), + DRAM_1_STAT_CATTRIP => hbmCatTripVec(1), + DRAM_0_STAT_TEMP => open, + DRAM_1_STAT_TEMP => open); + + hbmCatTrip <= uOr(hbmCatTripVec); + apbDone <= uAnd(apbDoneVec); + + U_apbDone : entity surf.Synchronizer + generic map ( + TPD_G => TPD_G) + port map ( + clk => axisClk, + dataIn => apbDone, + dataOut => apbDoneSync); + + U_axiReady : entity surf.RstPipelineVector + generic map ( + TPD_G => TPD_G, + WIDTH_G => 8, + INV_RST_G => false) + port map ( + clk => axisClk, + rstIn => (others => apbDoneSync), + rstOut => axiReady); + + U_apbRstL : entity surf.RstSync + generic map ( + TPD_G => TPD_G, + OUT_POLARITY_G => '0') -- active LOW + port map ( + clk => hbmRefClk, + asyncRst => axisRst, + syncRst => apbRstL); + +end mapping; diff --git a/hardware/XilinxVariumC1100/pcie-3x16/ruckus.tcl b/hardware/XilinxVariumC1100/pcie-3x16/ruckus.tcl index aa99487..3a6be1f 100644 --- a/hardware/XilinxVariumC1100/pcie-3x16/ruckus.tcl +++ b/hardware/XilinxVariumC1100/pcie-3x16/ruckus.tcl @@ -5,8 +5,9 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl" loadConstraints -dir "$::DIR_PATH/xdc" -# loadIpCore -path "$::DIR_PATH/ip/XilinxVariumC1100PciePhyGen3x16.xci" +loadIpCore -path "$::DIR_PATH/ip/HbmDmaBufferIpCore.xci" +# loadIpCore -path "$::DIR_PATH/ip/XilinxVariumC1100PciePhyGen3x16.xci" loadSource -lib axi_pcie_core -path "$::DIR_PATH/ip/XilinxVariumC1100PciePhyGen3x16.dcp" loadConstraints -path "$::DIR_PATH/ip/XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_gt.xdc" diff --git a/shared/ruckus.tcl b/shared/ruckus.tcl index d27c38c..d007239 100644 --- a/shared/ruckus.tcl +++ b/shared/ruckus.tcl @@ -3,8 +3,8 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Check for submodule tagging if { [info exists ::env(OVERRIDE_SUBMODULE_LOCKS)] != 1 || $::env(OVERRIDE_SUBMODULE_LOCKS) == 0 } { - if { [SubmoduleCheck {ruckus} {4.3.2} ] < 0 } {exit -1} - if { [SubmoduleCheck {surf} {2.31.0} ] < 0 } {exit -1} + if { [SubmoduleCheck {ruckus} {4.3.5} ] < 0 } {exit -1} + if { [SubmoduleCheck {surf} {2.33.0} ] < 0 } {exit -1} } else { puts "\n\n*********************************************************" puts "OVERRIDE_SUBMODULE_LOCKS != 0"