From 734dfe3a4aa946c50104e32a54c540ed69812ac8 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 14 Mar 2022 14:59:52 -0700 Subject: [PATCH 1/5] SI5394 dev --- .gitattributes | 19 +- .../Si5394_GTY_REFCLK_156p25MHz.csv | 503 ++++++++++++++++++ .../Si5394_GTY_REFCLK_156p25MHz.mem | 3 + .../Si5394_GTY_REFCLK_156p25MHz.slabtimeproj | 3 + .../XilinxAlveoU55c/misc/TerminateQsfp.vhd | 48 +- .../pcie-3x16/rtl/XilinxAlveoU55cCore.vhd | 47 +- hardware/XilinxAlveoU55c/pcie-3x16/ruckus.tcl | 1 - .../pcie-3x16/xdc/XilinxAlveoU55cTiming.xdc | 12 - hardware/XilinxAlveoU55c/ruckus.tcl | 3 + .../xdc/XilinxAlveoU55cApp.xdc | 33 +- .../xdc/XilinxAlveoU55cCore.xdc | 7 + .../XilinxVariumC1100/misc/AxiPciePkg.vhd | 38 -- .../XilinxVariumC1100/misc/TerminateQsfp.vhd | 199 ------- ...riumC1100PciePhyGen3x16_pcie4c_ip_late.xdc | 4 +- .../ip/ip_pcie4c_uscale_plus_impl_x1y1.xdc | 2 +- .../ip/ip_pcie4c_uscale_plus_x1y1.xdc | 8 +- .../pcie-3x16/rtl/XilinxVariumC1100Core.vhd | 97 +++- .../XilinxVariumC1100/pcie-3x16/ruckus.tcl | 1 - .../pcie-3x16/xdc/XilinxVariumC1100Timing.xdc | 12 - hardware/XilinxVariumC1100/ruckus.tcl | 9 +- .../xdc/XilinxVariumC1100App.xdc | 81 --- .../xdc/XilinxVariumC1100Core.xdc | 152 ------ python/axipcie/_AxiPcieCore.py | 9 + python/axipcie/_TerminateQsfp.py | 27 + python/axipcie/__init__.py | 13 +- 25 files changed, 746 insertions(+), 585 deletions(-) create mode 100644 hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv create mode 100644 hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem create mode 100644 hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj delete mode 100644 hardware/XilinxAlveoU55c/pcie-3x16/xdc/XilinxAlveoU55cTiming.xdc delete mode 100644 hardware/XilinxVariumC1100/misc/AxiPciePkg.vhd delete mode 100644 hardware/XilinxVariumC1100/misc/TerminateQsfp.vhd delete mode 100644 hardware/XilinxVariumC1100/pcie-3x16/xdc/XilinxVariumC1100Timing.xdc delete mode 100644 hardware/XilinxVariumC1100/xdc/XilinxVariumC1100App.xdc delete mode 100644 hardware/XilinxVariumC1100/xdc/XilinxVariumC1100Core.xdc create mode 100644 python/axipcie/_TerminateQsfp.py diff --git a/.gitattributes b/.gitattributes index 30006852..5be821e1 100644 --- a/.gitattributes +++ b/.gitattributes @@ -1,5 +1,18 @@ *.dcp filter=lfs diff=lfs merge=lfs -text -*.elf filter=lfs diff=lfs merge=lfs -text -*.bit filter=lfs diff=lfs merge=lfs -text -*.mcs filter=lfs diff=lfs merge=lfs -text *.gz filter=lfs diff=lfs merge=lfs -text +*.mcs filter=lfs diff=lfs merge=lfs -text +*.bin filter=lfs diff=lfs merge=lfs -text +*.bit filter=lfs diff=lfs merge=lfs -text +*.hdf filter=lfs diff=lfs merge=lfs -text +*.zip filter=lfs diff=lfs merge=lfs -text +*.ZIP filter=lfs diff=lfs merge=lfs -text +*.dat filter=lfs diff=lfs merge=lfs -text +*.hex filter=lfs diff=lfs merge=lfs -text +*.mem filter=lfs diff=lfs merge=lfs -text +*.pdi filter=lfs diff=lfs merge=lfs -text +*.bif filter=lfs diff=lfs merge=lfs -text +*.elf filter=lfs diff=lfs merge=lfs -text +*.slx filter=lfs diff=lfs merge=lfs -text +*.slabtimeproj filter=lfs diff=lfs merge=lfs -text +*.pptx filter=lfs diff=lfs merge=lfs -text +*.xlsx filter=lfs diff=lfs merge=lfs -text diff --git a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv new file mode 100644 index 00000000..5d6eeeb1 --- /dev/null +++ b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv @@ -0,0 +1,503 @@ +Address,Data +0x0006,0x00 +0x0007,0x00 +0x0008,0x00 +0x000B,0x68 +0x0016,0x02 +0x0017,0xDC +0x0018,0xFF +0x0019,0xFF +0x001A,0xFF +0x002B,0x0A +0x002C,0x00 +0x002D,0x00 +0x002E,0x00 +0x002F,0x00 +0x0030,0x00 +0x0031,0x00 +0x0032,0x00 +0x0033,0x00 +0x0034,0x00 +0x0035,0x00 +0x0036,0x00 +0x0037,0x00 +0x0038,0x00 +0x0039,0x00 +0x003A,0x00 +0x003B,0x00 +0x003C,0x00 +0x003D,0x00 +0x003E,0x00 +0x003F,0x00 +0x0040,0x04 +0x0041,0x00 +0x0042,0x00 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+0x0B4A,0x0C +0x0B57,0x0E +0x0B58,0x01 +0x0C02,0x03 +0x0C03,0x00 +0x0C07,0x00 +0x0C08,0x00 diff --git a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem new file mode 100644 index 00000000..58e07261 --- /dev/null +++ b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7f5f2b4506bfd2520601b91405b3114829ccacbc81379419ccff72dfa76c7178 +size 7168 diff --git a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj new file mode 100644 index 00000000..d8426dad --- /dev/null +++ b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:96d232cfb276219ce09338f00ac08080b665ca3ce1421973efce4ab040852c88 +size 11304 diff --git a/hardware/XilinxAlveoU55c/misc/TerminateQsfp.vhd b/hardware/XilinxAlveoU55c/misc/TerminateQsfp.vhd index 4864cd3e..baf41e0b 100644 --- a/hardware/XilinxAlveoU55c/misc/TerminateQsfp.vhd +++ b/hardware/XilinxAlveoU55c/misc/TerminateQsfp.vhd @@ -71,7 +71,7 @@ architecture mapping of TerminateQsfp is signal rin : RegType; signal unusedGtClk : slv(1 downto 0); - signal refClk : slv(1 downto 0); + signal refClk : slv(3 downto 0); signal refClkBufg : slv(3 downto 0); signal refClkFreq : Slv32Array(3 downto 0); @@ -105,30 +105,30 @@ begin gtTxN => qsfp1TxN); + U_unusedGtClk0 : IBUFDS_GTE4 + generic map ( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O + REFCLK_ICNTL_RX => "00") + port map ( + I => qsfp0RefClkP, + IB => qsfp0RefClkN, + CEB => '0', + ODIV2 => refClk(0), + O => unusedGtClk(0)); + + U_unusedGtClk1 : IBUFDS_GTE4 + generic map ( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O + REFCLK_ICNTL_RX => "00") + port map ( + I => qsfp1RefClkP, + IB => qsfp1RefClkN, + CEB => '0', + ODIV2 => refClk(1), + O => unusedGtClk(1)); - U_unusedGtClk0 : IBUFDS_GTE4 - generic map ( - REFCLK_EN_TX_PATH => '0', - REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O - REFCLK_ICNTL_RX => "00") - port map ( - I => qsfp0RefClkP, - IB => qsfp0RefClkN, - CEB => '0', - ODIV2 => refClk(0), - O => unusedGtClk(0)); - - U_unusedGtClk1 : IBUFDS_GTE4 - generic map ( - REFCLK_EN_TX_PATH => '0', - REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O - REFCLK_ICNTL_RX => "00") - port map ( - I => qsfp1RefClkP, - IB => qsfp1RefClkN, - CEB => '0', - ODIV2 => refClk(1), - O => unusedGtClk(1)); GEN_FREQ_MON : for i in 1 downto 0 generate diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd b/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd index d1cb5485..079aa4be 100644 --- a/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd +++ b/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd @@ -34,6 +34,7 @@ use unisim.vcomponents.all; entity XilinxAlveoU55cCore is generic ( TPD_G : time := 1 ns; + SI5394_INIT_FILE_G : string := "Si5394_GTY_REFCLK_156p25MHz.mem"; ROGUE_SIM_EN_G : boolean := false; ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000; ROGUE_SIM_CH_COUNT_G : natural range 1 to 256 := 256; @@ -71,8 +72,15 @@ entity XilinxAlveoU55cCore is -- Top Level Ports ------------------- -- System Ports - userClkP : in sl; - userClkN : in sl; + userClkP : in sl; + userClkN : in sl; + -- SI5394 Ports + si5394Scl : inout sl; + si5394Sda : inout sl; + si5394IrqL : in sl; + si5394LolL : in sl; + si5394LosL : in sl; + si5394RstL : out sl; -- PCIe Ports pciRstL : in sl; pciRefClkP : in slv(1 downto 0); @@ -105,6 +113,11 @@ architecture mapping of XilinxAlveoU55cCore is signal phyWriteMaster : AxiLiteWriteMasterType; signal phyWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C; + signal i2cReadMaster : AxiLiteReadMasterType; + signal i2cReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C; + signal i2cWriteMaster : AxiLiteWriteMasterType; + signal i2cWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C; + signal intPipIbMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; signal intPipIbSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; signal intPipObMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; @@ -188,6 +201,31 @@ begin pipIbMaster <= intPipIbMaster; intPipIbSlave <= pipIbSlave; + U_SI5394 : entity surf.Si5394I2c + generic map ( + TPD_G => TPD_G, + MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G, + I2C_BASE_ADDR_G => "00", + I2C_SCL_FREQ_G => 100.0E+3, -- units of Hz + AXIL_CLK_FREQ_G => DMA_CLK_FREQ_C) -- units of Hz + port map ( + -- I2C Ports + scl => si5394Scl, + sda => si5394Sda, + -- Misc Interface + irqL => si5394IrqL, + lolL => si5394LolL, + losL => si5394LosL, + rstL => si5394RstL, + -- AXI-Lite Register Interface + axilReadMaster => i2cReadMaster, + axilReadSlave => i2cReadSlave, + axilWriteMaster => i2cWriteMaster, + axilWriteSlave => i2cWriteSlave, + -- Clocks and Resets + axilClk => sysClock, + axilRst => sysReset); + end generate; SIM_PCIE : if (ROGUE_SIM_EN_G) generate @@ -243,6 +281,11 @@ begin phyReadSlave => phyReadSlave, phyWriteMaster => phyWriteMaster, phyWriteSlave => phyWriteSlave, + -- I2C AXI-Lite Interfaces (axiClk domain) + i2cReadMaster => i2cReadMaster, + i2cReadSlave => i2cReadSlave, + i2cWriteMaster => i2cWriteMaster, + i2cWriteSlave => i2cWriteSlave, -- (Optional) Application AXI-Lite Interfaces appClk => appClk, appRst => appRst, diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/ruckus.tcl b/hardware/XilinxAlveoU55c/pcie-3x16/ruckus.tcl index 056b7513..cee9c84d 100644 --- a/hardware/XilinxAlveoU55c/pcie-3x16/ruckus.tcl +++ b/hardware/XilinxAlveoU55c/pcie-3x16/ruckus.tcl @@ -3,7 +3,6 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load local Source Code and Constraints loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl" -loadConstraints -dir "$::DIR_PATH/xdc" # loadIpCore -path "$::DIR_PATH/ip/XilinxAlveoU55cPciePhyGen3x16.xci" diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/xdc/XilinxAlveoU55cTiming.xdc b/hardware/XilinxAlveoU55c/pcie-3x16/xdc/XilinxAlveoU55cTiming.xdc deleted file mode 100644 index 688fb798..00000000 --- a/hardware/XilinxAlveoU55c/pcie-3x16/xdc/XilinxAlveoU55cTiming.xdc +++ /dev/null @@ -1,12 +0,0 @@ -############################################################################## -## This file is part of 'axi-pcie-core'. -## It is subject to the license terms in the LICENSE.txt file found in the -## top-level directory of this distribution and at: -## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -## No part of 'axi-pcie-core', including this file, -## may be copied, modified, propagated, or distributed except according to -## the terms contained in the LICENSE.txt file. -############################################################################## - -set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClk0}] -group [get_clocks -include_generated_clocks {qsfp0RefClkP}] -set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClk0}] -group [get_clocks -include_generated_clocks {qsfp1RefClkP}] diff --git a/hardware/XilinxAlveoU55c/ruckus.tcl b/hardware/XilinxAlveoU55c/ruckus.tcl index 5289864e..3fc16279 100644 --- a/hardware/XilinxAlveoU55c/ruckus.tcl +++ b/hardware/XilinxAlveoU55c/ruckus.tcl @@ -33,3 +33,6 @@ loadConstraints -path "$::DIR_PATH/xdc/XilinxAlveoU55cApp.xdc" # Load the PCIe core loadRuckusTcl "$::DIR_PATH/${pcieType}" + +# Adding the common Si5345 configuration +add_files -norecurse "$::DIR_PATH/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem" diff --git a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc index a31c4150..217af029 100644 --- a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc +++ b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc @@ -11,12 +11,12 @@ # HBM Catastrophic Over temperature Output signal to Satellite Controller: active HIGH indicator to Satellite controller to indicate the HBM has exceeds its maximum allowable temperature. set_property -dict { PACKAGE_PIN BE45 IOSTANDARD LVCMOS18 PULLDOWN TRUE } [get_ports { hbmCatTrip }] -########### -# QSFP[0] # -########### +########################################## +# QSFP[0] - QSFP28 MGTY Interface QUAD 130 +########################################## -set_property PACKAGE_PIN AD42 [get_ports { qsfp0RefClkP }] ;# 161.1328125 MHz -set_property PACKAGE_PIN AD43 [get_ports { qsfp0RefClkN }] ;# 161.1328125 MHz +set_property PACKAGE_PIN AD42 [get_ports { qsfp0RefClkP }] ;# MGTREFCLK0P_130: 156.25 MHz (after reprogramming Si5394) +set_property PACKAGE_PIN AD43 [get_ports { qsfp0RefClkN }] ;# MGTREFCLK0N_130: 156.25 MHz (after reprogramming Si5394) set_property PACKAGE_PIN AD46 [get_ports { qsfp0TxP[0] }] set_property PACKAGE_PIN AD47 [get_ports { qsfp0TxN[0] }] @@ -38,12 +38,12 @@ set_property PACKAGE_PIN AA49 [get_ports { qsfp0TxN[3] }] set_property PACKAGE_PIN AB51 [get_ports { qsfp0RxP[3] }] set_property PACKAGE_PIN AB52 [get_ports { qsfp0RxN[3] }] -########### -# QSFP[1] # -########### +########################################## +# QSFP[0] - QSFP28 MGTY Interface QUAD 131 +########################################## -set_property PACKAGE_PIN AB42 [get_ports { qsfp1RefClkP }] ;# 161.1328125 MHz -set_property PACKAGE_PIN AB43 [get_ports { qsfp1RefClkN }] ;# 161.1328125 MHz +set_property PACKAGE_PIN AB42 [get_ports { qsfp1RefClkP }] ;# MGTREFCLK0P_131: 156.25 MHz (after reprogramming Si5394) +set_property PACKAGE_PIN AB43 [get_ports { qsfp1RefClkN }] ;# MGTREFCLK0N_131: 156.25 MHz (after reprogramming Si5394) set_property PACKAGE_PIN AA44 [get_ports { qsfp1TxP[0] }] set_property PACKAGE_PIN AA45 [get_ports { qsfp1TxN[0] }] @@ -70,12 +70,11 @@ set_property PACKAGE_PIN V52 [get_ports { qsfp1RxN[3] }] # Clocks # ########## -create_clock -period 6.206 -name qsfp0RefClkP [get_ports {qsfp0RefClkP}] ;# 161.1328125 MHz -create_clock -period 6.206 -name qsfp1RefClkP [get_ports {qsfp1RefClkP}] ;# 161.1328125 MHz +create_clock -period 6.4 -name qsfp0RefClkP [get_ports {qsfp0RefClkP}] ;# 156.25 MHz (after reprogramming Si5394) +create_clock -period 6.4 -name qsfp1RefClkP [get_ports {qsfp1RefClkP}] ;# 156.25 MHz (after reprogramming Si5394) -set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {userClkP}] -group [get_clocks -include_generated_clocks {qsfp0RefClkP}] -set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {userClkP}] -group [get_clocks -include_generated_clocks {qsfp1RefClkP}] - -set_clock_groups -asynchronous \ +set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {qsfp0RefClkP}] \ - -group [get_clocks -include_generated_clocks {qsfp1RefClkP}] + -group [get_clocks -include_generated_clocks {qsfp1RefClkP}] \ + -group [get_clocks -include_generated_clocks {pciRefClk0}] \ + -group [get_clocks -include_generated_clocks {userClkP}] diff --git a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc index 8c32520e..1e0cdbd7 100644 --- a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc +++ b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc @@ -19,6 +19,13 @@ set_operating_conditions -design_power_budget 63 set_property -dict { PACKAGE_PIN BK10 IOSTANDARD LVDS } [get_ports { userClkP }] set_property -dict { PACKAGE_PIN BL10 IOSTANDARD LVDS } [get_ports { userClkN }] +set_property -dict { PACKAGE_PIN BM14 IOSTANDARD LVCMOS18 } [get_ports { si5394Scl }] +set_property -dict { PACKAGE_PIN BN14 IOSTANDARD LVCMOS18 } [get_ports { si5394Sda }] +set_property -dict { PACKAGE_PIN BM9 IOSTANDARD LVCMOS18 } [get_ports { si5394IrqL }] +set_property -dict { PACKAGE_PIN BN10 IOSTANDARD LVCMOS18 } [get_ports { si5394LolL }] +set_property -dict { PACKAGE_PIN BM10 IOSTANDARD LVCMOS18 } [get_ports { si5394LosL }] +set_property -dict { PACKAGE_PIN BM8 IOSTANDARD LVCMOS18 } [get_ports { si5394RstL }] + #################### # PCIe Constraints # #################### diff --git a/hardware/XilinxVariumC1100/misc/AxiPciePkg.vhd b/hardware/XilinxVariumC1100/misc/AxiPciePkg.vhd deleted file mode 100644 index ef60eb74..00000000 --- a/hardware/XilinxVariumC1100/misc/AxiPciePkg.vhd +++ /dev/null @@ -1,38 +0,0 @@ -------------------------------------------------------------------------------- --- File : AxiPciePkg.vhd --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: Package file for AXI PCIe Core -------------------------------------------------------------------------------- --- This file is part of 'axi-pcie-core'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'axi-pcie-core', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -library surf; -use surf.StdRtlPkg.all; -use surf.AxiLitePkg.all; -use surf.AxiStreamPkg.all; -use surf.AxiPkg.all; - -package AxiPciePkg is - - -- System Clock Frequency - constant DMA_CLK_FREQ_C : real := 250.0E+6; -- units of Hz - - -- PCIE PHY AXI Configuration - constant AXI_PCIE_CONFIG_C : AxiConfigType := ( - ADDR_WIDTH_C => 40, -- 40-bit address interface - DATA_BYTES_C => 64, -- 512-bit data interface - ID_BITS_C => 4, -- Up to 16 DMA IDS - LEN_BITS_C => 8); -- 8-bit awlen/arlen interface - -end package AxiPciePkg; diff --git a/hardware/XilinxVariumC1100/misc/TerminateQsfp.vhd b/hardware/XilinxVariumC1100/misc/TerminateQsfp.vhd deleted file mode 100644 index 4864cd3e..00000000 --- a/hardware/XilinxVariumC1100/misc/TerminateQsfp.vhd +++ /dev/null @@ -1,199 +0,0 @@ -------------------------------------------------------------------------------- --- File : TerminateQsfp.vhd --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: TerminateQsfp File -------------------------------------------------------------------------------- --- This file is part of 'PGP PCIe APP DEV'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'PGP PCIe APP DEV', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - - -library surf; -use surf.StdRtlPkg.all; -use surf.AxiLitePkg.all; - -library unisim; -use unisim.vcomponents.all; - -entity TerminateQsfp is - generic ( - TPD_G : time := 1 ns; - AXIL_CLK_FREQ_G : real := 156.25E+6); -- units of Hz - port ( - -- AXI-Lite Interface - axilClk : in sl; - axilRst : in sl; - axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - axilReadSlave : out AxiLiteReadSlaveType; - axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - axilWriteSlave : out AxiLiteWriteSlaveType; - --------------------- - -- Application Ports - --------------------- - -- QSFP[0] Ports - qsfp0RefClkP : in sl; - qsfp0RefClkN : in sl; - qsfp0RxP : in slv(3 downto 0); - qsfp0RxN : in slv(3 downto 0); - qsfp0TxP : out slv(3 downto 0); - qsfp0TxN : out slv(3 downto 0); - -- QSFP[1] Ports - qsfp1RefClkP : in sl; - qsfp1RefClkN : in sl; - qsfp1RxP : in slv(3 downto 0); - qsfp1RxN : in slv(3 downto 0); - qsfp1TxP : out slv(3 downto 0); - qsfp1TxN : out slv(3 downto 0)); -end TerminateQsfp; - -architecture mapping of TerminateQsfp is - - type RegType is record - axilReadSlave : AxiLiteReadSlaveType; - axilWriteSlave : AxiLiteWriteSlaveType; - end record; - constant REG_INIT_C : RegType := ( - axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, - axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C); - - signal r : RegType := REG_INIT_C; - signal rin : RegType; - - signal unusedGtClk : slv(1 downto 0); - signal refClk : slv(1 downto 0); - signal refClkBufg : slv(3 downto 0); - signal refClkFreq : Slv32Array(3 downto 0); - - attribute dont_touch : string; - attribute dont_touch of unusedGtClk : signal is "TRUE"; - -begin - - -- Unused QSFP Port - U_QSFP0 : entity surf.Gtye4ChannelDummy - generic map ( - TPD_G => TPD_G, - WIDTH_G => 4) - port map ( - refClk => axilClk, - gtRxP => qsfp0RxP, - gtRxN => qsfp0RxN, - gtTxP => qsfp0TxP, - gtTxN => qsfp0TxN); - - -- Unused QSFP Port - U_QSFP1 : entity surf.Gtye4ChannelDummy - generic map ( - TPD_G => TPD_G, - WIDTH_G => 4) - port map ( - refClk => axilClk, - gtRxP => qsfp1RxP, - gtRxN => qsfp1RxN, - gtTxP => qsfp1TxP, - gtTxN => qsfp1TxN); - - - - U_unusedGtClk0 : IBUFDS_GTE4 - generic map ( - REFCLK_EN_TX_PATH => '0', - REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O - REFCLK_ICNTL_RX => "00") - port map ( - I => qsfp0RefClkP, - IB => qsfp0RefClkN, - CEB => '0', - ODIV2 => refClk(0), - O => unusedGtClk(0)); - - U_unusedGtClk1 : IBUFDS_GTE4 - generic map ( - REFCLK_EN_TX_PATH => '0', - REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O - REFCLK_ICNTL_RX => "00") - port map ( - I => qsfp1RefClkP, - IB => qsfp1RefClkN, - CEB => '0', - ODIV2 => refClk(1), - O => unusedGtClk(1)); - - GEN_FREQ_MON : for i in 1 downto 0 generate - - U_BUFG : BUFG_GT - port map ( - I => refClk(i), - CE => '1', - CEMASK => '1', - CLR => '0', - CLRMASK => '1', - DIV => "000", -- Divide-by-1 - O => refClkBufg(i)); - - U_appClkFreq : entity surf.SyncClockFreq - generic map ( - TPD_G => TPD_G, - REF_CLK_FREQ_G => AXIL_CLK_FREQ_G, - REFRESH_RATE_G => 1.0, - CNT_WIDTH_G => 32) - port map ( - -- Frequency Measurement (locClk domain) - freqOut => refClkFreq(i), - -- Clocks - clkIn => refClkBufg(i), - locClk => axilClk, - refClk => axilClk); - - end generate GEN_FREQ_MON; - - comb : process (axilReadMaster, axilRst, axilWriteMaster, r, refClkFreq) is - variable v : RegType; - variable axilEp : AxiLiteEndPointType; - begin - -- Latch the current value - v := r; - - -- Determine the transaction type - axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave); - - -- Map the read registers - axiSlaveRegisterR(axilEp, x"0", 0, refClkFreq(0)); - axiSlaveRegisterR(axilEp, x"4", 0, refClkFreq(1)); - - -- Closeout the transaction - axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); - - -- Outputs - axilWriteSlave <= r.axilWriteSlave; - axilReadSlave <= r.axilReadSlave; - - -- Reset - if (axilRst = '1') then - v := REG_INIT_C; - end if; - - -- Register the variable for next clock cycle - rin <= v; - - end process comb; - - seq : process (axilClk) is - begin - if rising_edge(axilClk) then - r <= rin after TPD_G; - end if; - end process seq; - -end mapping; diff --git a/hardware/XilinxVariumC1100/pcie-3x16/ip/XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_late.xdc b/hardware/XilinxVariumC1100/pcie-3x16/ip/XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_late.xdc index 3fc5d2d7..90f35e0d 100644 --- a/hardware/XilinxVariumC1100/pcie-3x16/ip/XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_late.xdc +++ b/hardware/XilinxVariumC1100/pcie-3x16/ip/XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_late.xdc @@ -50,10 +50,10 @@ ## ## Project : UltraScale+ FPGA PCI Express CCIX v4.0 Integrated Block ## File : XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_late.xdc -## Version : 1.0 +## Version : 1.0 ##----------------------------------------------------------------------------- # -# This constraints file contains ASYNC clock grouping and processed late after OOC and IP Level XDC files. +# This constraints file contains ASYNC clock grouping and processed late after OOC and IP Level XDC files. # # ############################################################################### diff --git a/hardware/XilinxVariumC1100/pcie-3x16/ip/ip_pcie4c_uscale_plus_impl_x1y1.xdc b/hardware/XilinxVariumC1100/pcie-3x16/ip/ip_pcie4c_uscale_plus_impl_x1y1.xdc index 6301300a..7200a82e 100644 --- a/hardware/XilinxVariumC1100/pcie-3x16/ip/ip_pcie4c_uscale_plus_impl_x1y1.xdc +++ b/hardware/XilinxVariumC1100/pcie-3x16/ip/ip_pcie4c_uscale_plus_impl_x1y1.xdc @@ -50,7 +50,7 @@ ## ## Project : UltraScale+ FPGA PCI Express CCIX v4.0 Integrated Block ## File : ip_pcie4c_uscale_plus_impl_x1y1.xdc -## Version : 1.0 +## Version : 1.0 ##----------------------------------------------------------------------------- # ############################################################################### diff --git a/hardware/XilinxVariumC1100/pcie-3x16/ip/ip_pcie4c_uscale_plus_x1y1.xdc b/hardware/XilinxVariumC1100/pcie-3x16/ip/ip_pcie4c_uscale_plus_x1y1.xdc index 67beffb9..c5202a03 100644 --- a/hardware/XilinxVariumC1100/pcie-3x16/ip/ip_pcie4c_uscale_plus_x1y1.xdc +++ b/hardware/XilinxVariumC1100/pcie-3x16/ip/ip_pcie4c_uscale_plus_x1y1.xdc @@ -50,12 +50,12 @@ ## ## Project : UltraScale+ FPGA PCI Express CCIX v4.0 Integrated Block ## File : ip_pcie4c_uscale_plus_x1y1.xdc -## Version : 1.0 +## Version : 1.0 ##----------------------------------------------------------------------------- # # pcie_blk_locn_int - X7 ############################################################################### -# Vivado - PCIe GUI / User Configuration +# Vivado - PCIe GUI / User Configuration ############################################################################### # # Family - virtexuplusHBM @@ -111,10 +111,10 @@ set_property LOC PCIE4CE4_X1Y1 [get_cells XilinxVariumC1100PciePhyGen3x16_pcie4c # TXOUTCLK Constraint ############################################################################### # -# Constraining GT TXOUTCLK to 500 MHz +# Constraining GT TXOUTCLK to 500 MHz #create_clock -period 2.0 [get_pins -filter {REF_PIN_NAME=~TXOUTCLK} -of_objects [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[27].*gen_gtye4_channel_inst[3].GT*E4_CHANNEL_PRIM_INST}]] # -# This is a slow running clock 1MHz drives small logic before perst only for delaying reference clock probation. +# This is a slow running clock 1MHz drives small logic before perst only for delaying reference clock probation. create_clock -period 1000 [get_pins XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O] # # diff --git a/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd b/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd index b0e08c4e..c118e72d 100644 --- a/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd +++ b/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd @@ -34,6 +34,7 @@ use unisim.vcomponents.all; entity XilinxVariumC1100Core is generic ( TPD_G : time := 1 ns; + SI5394_INIT_FILE_G : string := "Si5394_GTY_REFCLK_156p25MHz.mem"; ROGUE_SIM_EN_G : boolean := false; ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000; ROGUE_SIM_CH_COUNT_G : natural range 1 to 256 := 256; @@ -46,41 +47,48 @@ entity XilinxVariumC1100Core is ------------------------ -- Top Level Interfaces ------------------------ - userClk100 : out sl; + userClk100 : out sl; -- DMA Interfaces (dmaClk domain) - dmaClk : out sl; - dmaRst : out sl; - dmaBuffGrpPause : out slv(7 downto 0); - dmaObMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); - dmaObSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); - dmaIbMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); - dmaIbSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + dmaClk : out sl; + dmaRst : out sl; + dmaBuffGrpPause : out slv(7 downto 0); + dmaObMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + dmaObSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + dmaIbMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + dmaIbSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); -- PIP Interface [0x00080000:0009FFFF] (dmaClk domain) - pipIbMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - pipIbSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; - pipObMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - pipObSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; + pipIbMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + pipIbSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; + pipObMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + pipObSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; -- Application AXI-Lite Interfaces [0x00100000:0x00FFFFFF] (appClk domain) - appClk : in sl := '0'; - appRst : in sl := '1'; - appReadMaster : out AxiLiteReadMasterType; - appReadSlave : in AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C; - appWriteMaster : out AxiLiteWriteMasterType; - appWriteSlave : in AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C; + appClk : in sl := '0'; + appRst : in sl := '1'; + appReadMaster : out AxiLiteReadMasterType; + appReadSlave : in AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C; + appWriteMaster : out AxiLiteWriteMasterType; + appWriteSlave : in AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C; ------------------- -- Top Level Ports ------------------- -- System Ports - userClkP : in sl; - userClkN : in sl; + userClkP : in sl; + userClkN : in sl; + -- SI5394 Ports + si5394Scl : inout sl; + si5394Sda : inout sl; + si5394IrqL : in sl; + si5394LolL : in sl; + si5394LosL : in sl; + si5394RstL : out sl; -- PCIe Ports - pciRstL : in sl; - pciRefClkP : in slv(1 downto 0); - pciRefClkN : in slv(1 downto 0); - pciRxP : in slv(15 downto 0); - pciRxN : in slv(15 downto 0); - pciTxP : out slv(15 downto 0); - pciTxN : out slv(15 downto 0)); + pciRstL : in sl; + pciRefClkP : in slv(1 downto 0); + pciRefClkN : in slv(1 downto 0); + pciRxP : in slv(15 downto 0); + pciRxN : in slv(15 downto 0); + pciTxP : out slv(15 downto 0); + pciTxN : out slv(15 downto 0)); end XilinxVariumC1100Core; architecture mapping of XilinxVariumC1100Core is @@ -105,6 +113,11 @@ architecture mapping of XilinxVariumC1100Core is signal phyWriteMaster : AxiLiteWriteMasterType; signal phyWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C; + signal i2cReadMaster : AxiLiteReadMasterType; + signal i2cReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C; + signal i2cWriteMaster : AxiLiteWriteMasterType; + signal i2cWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C; + signal intPipIbMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; signal intPipIbSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; signal intPipObMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; @@ -188,6 +201,31 @@ begin pipIbMaster <= intPipIbMaster; intPipIbSlave <= pipIbSlave; + U_SI5394 : entity surf.Si5394I2c + generic map ( + TPD_G => TPD_G, + MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G, + I2C_BASE_ADDR_G => "00", + I2C_SCL_FREQ_G => 100.0E+3, -- units of Hz + AXIL_CLK_FREQ_G => DMA_CLK_FREQ_C) -- units of Hz + port map ( + -- I2C Ports + scl => si5394Scl, + sda => si5394Sda, + -- Misc Interface + irqL => si5394IrqL, + lolL => si5394LolL, + losL => si5394LosL, + rstL => si5394RstL, + -- AXI-Lite Register Interface + axilReadMaster => i2cReadMaster, + axilReadSlave => i2cReadSlave, + axilWriteMaster => i2cWriteMaster, + axilWriteSlave => i2cWriteSlave, + -- Clocks and Resets + axilClk => sysClock, + axilRst => sysReset); + end generate; SIM_PCIE : if (ROGUE_SIM_EN_G) generate @@ -243,6 +281,11 @@ begin phyReadSlave => phyReadSlave, phyWriteMaster => phyWriteMaster, phyWriteSlave => phyWriteSlave, + -- I2C AXI-Lite Interfaces (axiClk domain) + i2cReadMaster => i2cReadMaster, + i2cReadSlave => i2cReadSlave, + i2cWriteMaster => i2cWriteMaster, + i2cWriteSlave => i2cWriteSlave, -- (Optional) Application AXI-Lite Interfaces appClk => appClk, appRst => appRst, diff --git a/hardware/XilinxVariumC1100/pcie-3x16/ruckus.tcl b/hardware/XilinxVariumC1100/pcie-3x16/ruckus.tcl index aa994872..6fe55bbe 100644 --- a/hardware/XilinxVariumC1100/pcie-3x16/ruckus.tcl +++ b/hardware/XilinxVariumC1100/pcie-3x16/ruckus.tcl @@ -3,7 +3,6 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load local Source Code and Constraints loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl" -loadConstraints -dir "$::DIR_PATH/xdc" # loadIpCore -path "$::DIR_PATH/ip/XilinxVariumC1100PciePhyGen3x16.xci" diff --git a/hardware/XilinxVariumC1100/pcie-3x16/xdc/XilinxVariumC1100Timing.xdc b/hardware/XilinxVariumC1100/pcie-3x16/xdc/XilinxVariumC1100Timing.xdc deleted file mode 100644 index 688fb798..00000000 --- a/hardware/XilinxVariumC1100/pcie-3x16/xdc/XilinxVariumC1100Timing.xdc +++ /dev/null @@ -1,12 +0,0 @@ -############################################################################## -## This file is part of 'axi-pcie-core'. -## It is subject to the license terms in the LICENSE.txt file found in the -## top-level directory of this distribution and at: -## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -## No part of 'axi-pcie-core', including this file, -## may be copied, modified, propagated, or distributed except according to -## the terms contained in the LICENSE.txt file. -############################################################################## - -set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClk0}] -group [get_clocks -include_generated_clocks {qsfp0RefClkP}] -set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClk0}] -group [get_clocks -include_generated_clocks {qsfp1RefClkP}] diff --git a/hardware/XilinxVariumC1100/ruckus.tcl b/hardware/XilinxVariumC1100/ruckus.tcl index ea3cf866..1a3df07c 100644 --- a/hardware/XilinxVariumC1100/ruckus.tcl +++ b/hardware/XilinxVariumC1100/ruckus.tcl @@ -27,9 +27,12 @@ if { [info exists ::env(BUILD_PCIE_GEN4)] != 1 || $::env(BUILD_PCIE_GEN4) == 0 } } # Load local Source Code and Constraints -loadSource -lib axi_pcie_core -dir "$::DIR_PATH/misc" -loadConstraints -path "$::DIR_PATH/xdc/XilinxVariumC1100Core.xdc" -loadConstraints -path "$::DIR_PATH/xdc/XilinxVariumC1100App.xdc" +loadSource -lib axi_pcie_core -dir "$::DIR_PATH/../XilinxAlveoU55c/misc" +loadConstraints -path "$::DIR_PATH/../XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc" +loadConstraints -path "$::DIR_PATH/../XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc" # Load the PCIe core loadRuckusTcl "$::DIR_PATH/${pcieType}" + +# Adding the common Si5345 configuration +add_files -norecurse "$::DIR_PATH/../XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem" diff --git a/hardware/XilinxVariumC1100/xdc/XilinxVariumC1100App.xdc b/hardware/XilinxVariumC1100/xdc/XilinxVariumC1100App.xdc deleted file mode 100644 index a31c4150..00000000 --- a/hardware/XilinxVariumC1100/xdc/XilinxVariumC1100App.xdc +++ /dev/null @@ -1,81 +0,0 @@ -############################################################################## -## This file is part of 'axi-pcie-core'. -## It is subject to the license terms in the LICENSE.txt file found in the -## top-level directory of this distribution and at: -## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -## No part of 'axi-pcie-core', including this file, -## may be copied, modified, propagated, or distributed except according to -## the terms contained in the LICENSE.txt file. -############################################################################## - -# HBM Catastrophic Over temperature Output signal to Satellite Controller: active HIGH indicator to Satellite controller to indicate the HBM has exceeds its maximum allowable temperature. -set_property -dict { PACKAGE_PIN BE45 IOSTANDARD LVCMOS18 PULLDOWN TRUE } [get_ports { hbmCatTrip }] - -########### -# QSFP[0] # -########### - -set_property PACKAGE_PIN AD42 [get_ports { qsfp0RefClkP }] ;# 161.1328125 MHz -set_property PACKAGE_PIN AD43 [get_ports { qsfp0RefClkN }] ;# 161.1328125 MHz - -set_property PACKAGE_PIN AD46 [get_ports { qsfp0TxP[0] }] -set_property PACKAGE_PIN AD47 [get_ports { qsfp0TxN[0] }] -set_property PACKAGE_PIN AD51 [get_ports { qsfp0RxP[0] }] -set_property PACKAGE_PIN AD52 [get_ports { qsfp0RxN[0] }] - -set_property PACKAGE_PIN AC44 [get_ports { qsfp0TxP[1] }] -set_property PACKAGE_PIN AC45 [get_ports { qsfp0TxN[1] }] -set_property PACKAGE_PIN AC53 [get_ports { qsfp0RxP[1] }] -set_property PACKAGE_PIN AC54 [get_ports { qsfp0RxN[1] }] - -set_property PACKAGE_PIN AB46 [get_ports { qsfp0TxP[2] }] -set_property PACKAGE_PIN AB47 [get_ports { qsfp0TxN[2] }] -set_property PACKAGE_PIN AC49 [get_ports { qsfp0RxP[2] }] -set_property PACKAGE_PIN AC50 [get_ports { qsfp0RxN[2] }] - -set_property PACKAGE_PIN AA48 [get_ports { qsfp0TxP[3] }] -set_property PACKAGE_PIN AA49 [get_ports { qsfp0TxN[3] }] -set_property PACKAGE_PIN AB51 [get_ports { qsfp0RxP[3] }] -set_property PACKAGE_PIN AB52 [get_ports { qsfp0RxN[3] }] - -########### -# QSFP[1] # -########### - -set_property PACKAGE_PIN AB42 [get_ports { qsfp1RefClkP }] ;# 161.1328125 MHz -set_property PACKAGE_PIN AB43 [get_ports { qsfp1RefClkN }] ;# 161.1328125 MHz - -set_property PACKAGE_PIN AA44 [get_ports { qsfp1TxP[0] }] -set_property PACKAGE_PIN AA45 [get_ports { qsfp1TxN[0] }] -set_property PACKAGE_PIN AA53 [get_ports { qsfp1RxP[0] }] -set_property PACKAGE_PIN AA54 [get_ports { qsfp1RxN[0] }] - -set_property PACKAGE_PIN Y46 [get_ports { qsfp1TxP[1] }] -set_property PACKAGE_PIN Y47 [get_ports { qsfp1TxN[1] }] -set_property PACKAGE_PIN Y51 [get_ports { qsfp1RxP[1] }] -set_property PACKAGE_PIN Y52 [get_ports { qsfp1RxN[1] }] - -set_property PACKAGE_PIN W48 [get_ports { qsfp1TxP[2] }] -set_property PACKAGE_PIN W49 [get_ports { qsfp1TxN[2] }] -set_property PACKAGE_PIN W53 [get_ports { qsfp1RxP[2] }] -set_property PACKAGE_PIN W54 [get_ports { qsfp1RxN[2] }] - -set_property PACKAGE_PIN W44 [get_ports { qsfp1TxP[3] }] -set_property PACKAGE_PIN W45 [get_ports { qsfp1TxN[3] }] -set_property PACKAGE_PIN V51 [get_ports { qsfp1RxP[3] }] -set_property PACKAGE_PIN V52 [get_ports { qsfp1RxN[3] }] - - -########## -# Clocks # -########## - -create_clock -period 6.206 -name qsfp0RefClkP [get_ports {qsfp0RefClkP}] ;# 161.1328125 MHz -create_clock -period 6.206 -name qsfp1RefClkP [get_ports {qsfp1RefClkP}] ;# 161.1328125 MHz - -set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {userClkP}] -group [get_clocks -include_generated_clocks {qsfp0RefClkP}] -set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {userClkP}] -group [get_clocks -include_generated_clocks {qsfp1RefClkP}] - -set_clock_groups -asynchronous \ - -group [get_clocks -include_generated_clocks {qsfp0RefClkP}] \ - -group [get_clocks -include_generated_clocks {qsfp1RefClkP}] diff --git a/hardware/XilinxVariumC1100/xdc/XilinxVariumC1100Core.xdc b/hardware/XilinxVariumC1100/xdc/XilinxVariumC1100Core.xdc deleted file mode 100644 index 79c9ad8d..00000000 --- a/hardware/XilinxVariumC1100/xdc/XilinxVariumC1100Core.xdc +++ /dev/null @@ -1,152 +0,0 @@ -############################################################################## -## This file is part of 'axi-pcie-core'. -## It is subject to the license terms in the LICENSE.txt file found in the -## top-level directory of this distribution and at: -## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -## No part of 'axi-pcie-core', including this file, -## may be copied, modified, propagated, or distributed except according to -## the terms contained in the LICENSE.txt file. -############################################################################## - -# set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_Core}] - -set_operating_conditions -design_power_budget 63 - -########## -# System # -########## - -set_property -dict { PACKAGE_PIN BK10 IOSTANDARD LVDS } [get_ports { userClkP }] -set_property -dict { PACKAGE_PIN BL10 IOSTANDARD LVDS } [get_ports { userClkN }] - -#################### -# PCIe Constraints # -#################### - -set_property PACKAGE_PIN BC1 [get_ports {pciRxN[15]}] ;# Bank 224 - MGTYRXN0_224 -set_property PACKAGE_PIN BB3 [get_ports {pciRxN[14]}] ;# Bank 224 - MGTYRXN1_224 -set_property PACKAGE_PIN BA1 [get_ports {pciRxN[13]}] ;# Bank 224 - MGTYRXN2_224 -set_property PACKAGE_PIN BA5 [get_ports {pciRxN[12]}] ;# Bank 224 - MGTYRXN3_224 - -set_property PACKAGE_PIN BC2 [get_ports {pciRxP[15]}] ;# Bank 224 - MGTYRXP0_224 -set_property PACKAGE_PIN BB4 [get_ports {pciRxP[14]}] ;# Bank 224 - MGTYRXP1_224 -set_property PACKAGE_PIN BA2 [get_ports {pciRxP[13]}] ;# Bank 224 - MGTYRXP2_224 -set_property PACKAGE_PIN BA6 [get_ports {pciRxP[12]}] ;# Bank 224 - MGTYRXP3_224 - -set_property PACKAGE_PIN BC6 [get_ports {pciTxN[15]}] ;# Bank 224 - MGTYTXN0_224 -set_property PACKAGE_PIN BC10 [get_ports {pciTxN[14]}] ;# Bank 224 - MGTYTXN1_224 -set_property PACKAGE_PIN BB8 [get_ports {pciTxN[13]}] ;# Bank 224 - MGTYTXN2_224 -set_property PACKAGE_PIN BA10 [get_ports {pciTxN[12]}] ;# Bank 224 - MGTYTXN3_224 - -set_property PACKAGE_PIN BC7 [get_ports {pciTxP[15]}] ;# Bank 224 - MGTYTXP0_224 -set_property PACKAGE_PIN BC11 [get_ports {pciTxP[14]}] ;# Bank 224 - MGTYTXP1_224 -set_property PACKAGE_PIN BB9 [get_ports {pciTxP[13]}] ;# Bank 224 - MGTYTXP2_224 -set_property PACKAGE_PIN BA11 [get_ports {pciTxP[12]}] ;# Bank 224 - MGTYTXP3_224 - -set_property PACKAGE_PIN AY3 [get_ports {pciRxN[11]}] ;# Bank 225 - MGTYRXN0_225 -set_property PACKAGE_PIN AW1 [get_ports {pciRxN[10]}] ;# Bank 225 - MGTYRXN1_225 -set_property PACKAGE_PIN AW5 [get_ports {pciRxN[9]}] ;# Bank 225 - MGTYRXN2_225 -set_property PACKAGE_PIN AV3 [get_ports {pciRxN[8]}] ;# Bank 225 - MGTYRXN3_225 - -set_property PACKAGE_PIN AY4 [get_ports {pciRxP[11]}] ;# Bank 225 - MGTYRXP0_225 -set_property PACKAGE_PIN AW2 [get_ports {pciRxP[10]}] ;# Bank 225 - MGTYRXP1_225 -set_property PACKAGE_PIN AW6 [get_ports {pciRxP[9]}] ;# Bank 225 - MGTYRXP2_225 -set_property PACKAGE_PIN AV4 [get_ports {pciRxP[8]}] ;# Bank 225 - MGTYRXP3_225 - -set_property PACKAGE_PIN AY8 [get_ports {pciTxN[11]}] ;# Bank 225 - MGTYTXN0_225 -set_property PACKAGE_PIN AW10 [get_ports {pciTxN[10]}] ;# Bank 225 - MGTYTXN1_225 -set_property PACKAGE_PIN AV8 [get_ports {pciTxN[9]}] ;# Bank 225 - MGTYTXN2_225 -set_property PACKAGE_PIN AU6 [get_ports {pciTxN[8]}] ;# Bank 225 - MGTYTXN3_225 - -set_property PACKAGE_PIN AY9 [get_ports {pciTxP[11]}] ;# Bank 225 - MGTYTXP0_225 -set_property PACKAGE_PIN AW11 [get_ports {pciTxP[10]}] ;# Bank 225 - MGTYTXP1_225 -set_property PACKAGE_PIN AV9 [get_ports {pciTxP[9]}] ;# Bank 225 - MGTYTXP2_225 -set_property PACKAGE_PIN AU7 [get_ports {pciTxP[8]}] ;# Bank 225 - MGTYTXP3_225 - -set_property PACKAGE_PIN AU1 [get_ports {pciRxN[7]}] ;# Bank 226 - MGTYRXN0_226 -set_property PACKAGE_PIN AT3 [get_ports {pciRxN[6]}] ;# Bank 226 - MGTYRXN1_226 -set_property PACKAGE_PIN AR1 [get_ports {pciRxN[5]}] ;# Bank 226 - MGTYRXN2_226 -set_property PACKAGE_PIN AP3 [get_ports {pciRxN[4]}] ;# Bank 226 - MGTYRXN3_226 - -set_property PACKAGE_PIN AU2 [get_ports {pciRxP[7]}] ;# Bank 226 - MGTYRXP0_226 -set_property PACKAGE_PIN AT4 [get_ports {pciRxP[6]}] ;# Bank 226 - MGTYRXP1_226 -set_property PACKAGE_PIN AR2 [get_ports {pciRxP[5]}] ;# Bank 226 - MGTYRXP2_226 -set_property PACKAGE_PIN AP4 [get_ports {pciRxP[4]}] ;# Bank 226 - MGTYRXP3_226 - -set_property PACKAGE_PIN AU10 [get_ports {pciTxN[7]}] ;# Bank 226 - MGTYTXN0_226 -set_property PACKAGE_PIN AT8 [get_ports {pciTxN[6]}] ;# Bank 226 - MGTYTXN1_226 -set_property PACKAGE_PIN AR6 [get_ports {pciTxN[5]}] ;# Bank 226 - MGTYTXN2_226 -set_property PACKAGE_PIN AR10 [get_ports {pciTxN[4]}] ;# Bank 226 - MGTYTXN3_226 - -set_property PACKAGE_PIN AU11 [get_ports {pciTxP[7]}] ;# Bank 226 - MGTYTXP0_226 -set_property PACKAGE_PIN AT9 [get_ports {pciTxP[6]}] ;# Bank 226 - MGTYTXP1_226 -set_property PACKAGE_PIN AR7 [get_ports {pciTxP[5]}] ;# Bank 226 - MGTYTXP2_226 -set_property PACKAGE_PIN AR11 [get_ports {pciTxP[4]}] ;# Bank 226 - MGTYTXP3_226 - -set_property PACKAGE_PIN AN1 [get_ports {pciRxN[3]}] ;# Bank 227 - MGTYRXN0_227 -set_property PACKAGE_PIN AN5 [get_ports {pciRxN[2]}] ;# Bank 227 - MGTYRXN1_227 -set_property PACKAGE_PIN AM3 [get_ports {pciRxN[1]}] ;# Bank 227 - MGTYRXN2_227 -set_property PACKAGE_PIN AL1 [get_ports {pciRxN[0]}] ;# Bank 227 - MGTYRXN3_227 - -set_property PACKAGE_PIN AN2 [get_ports {pciRxP[3]}] ;# Bank 227 - MGTYRXP0_227 -set_property PACKAGE_PIN AN6 [get_ports {pciRxP[2]}] ;# Bank 227 - MGTYRXP1_227 -set_property PACKAGE_PIN AM4 [get_ports {pciRxP[1]}] ;# Bank 227 - MGTYRXP2_227 -set_property PACKAGE_PIN AL2 [get_ports {pciRxP[0]}] ;# Bank 227 - MGTYRXP3_227 - -set_property PACKAGE_PIN AP8 [get_ports {pciTxN[3]}] ;# Bank 227 - MGTYTXN0_227 -set_property PACKAGE_PIN AN10 [get_ports {pciTxN[2]}] ;# Bank 227 - MGTYTXN1_227 -set_property PACKAGE_PIN AM8 [get_ports {pciTxN[1]}] ;# Bank 227 - MGTYTXN2_227 -set_property PACKAGE_PIN AL10 [get_ports {pciTxN[0]}] ;# Bank 227 - MGTYTXN3_227 - -set_property PACKAGE_PIN AP9 [get_ports {pciTxP[3]}] ;# Bank 227 - MGTYTXP0_227 -set_property PACKAGE_PIN AN11 [get_ports {pciTxP[2]}] ;# Bank 227 - MGTYTXP1_227 -set_property PACKAGE_PIN AM9 [get_ports {pciTxP[1]}] ;# Bank 227 - MGTYTXP2_227 -set_property PACKAGE_PIN AL11 [get_ports {pciTxP[0]}] ;# Bank 227 - MGTYTXP3_227 - -set_property PACKAGE_PIN AL15 [get_ports {pciRefClkP[1]}] -set_property PACKAGE_PIN AL14 [get_ports {pciRefClkN[1]}] - -set_property PACKAGE_PIN AR15 [get_ports {pciRefClkP[0]}] -set_property PACKAGE_PIN AR14 [get_ports {pciRefClkN[0]}] - -set_property -dict { PACKAGE_PIN BF41 IOSTANDARD LVCMOS18 } [get_ports {pciRstL}] -set_false_path -from [get_ports pciRstL] -set_property PULLUP true [get_ports pciRstL] - -########## -# Clocks # -########## - -create_clock -period 10.000 -name pciRefClk0 [get_ports {pciRefClkP[0]}] -create_clock -period 10.000 -name pciRefClk1 [get_ports {pciRefClkP[1]}] -create_clock -period 10.000 -name userClkP [get_ports {userClkP}] -create_clock -period 16.000 -name dnaClk [get_pins {U_Core/U_REG/U_Version/GEN_DEVICE_DNA.DeviceDna_1/GEN_ULTRA_SCALE.DeviceDnaUltraScale_Inst/BUFGCE_DIV_Inst/O}] -create_clock -period 16.000 -name iprogClk [get_pins {U_Core/U_REG/U_Version/GEN_ICAP.Iprog_1/GEN_ULTRA_SCALE.IprogUltraScale_Inst/BUFGCE_DIV_Inst/O}] - -set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClk0}] -group [get_clocks -include_generated_clocks {userClkP}] -set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClk1}] -group [get_clocks -include_generated_clocks {userClkP}] - -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks dnaClk] -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks iprogClk] -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks -of_objects [get_pins U_axilClk/PllGen.U_Pll/CLKOUT0] - -set_false_path -to [get_pins -hier *sync_reg[0]/D] - -set_false_path -from [get_ports {pciRstL}] - -set_property HIGH_PRIORITY true [get_nets {U_Core/REAL_PCIE.U_AxiPciePhy/axiClk}] - -###################################### -# BITSTREAM: .bit file Configuration # -###################################### - -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] ;# Golden image is the fall back image if new bitstream is corrupted. -set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] -set_property CONFIG_MODE SPIx4 [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] ;# Choices are pullnone, pulldown, and pullup. -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] diff --git a/python/axipcie/_AxiPcieCore.py b/python/axipcie/_AxiPcieCore.py index df00ddaf..ce4f05c8 100644 --- a/python/axipcie/_AxiPcieCore.py +++ b/python/axipcie/_AxiPcieCore.py @@ -12,6 +12,7 @@ import surf.axi as axi import surf.devices.micron as micron import surf.devices.nxp as nxp +import surf.devices.silabs as silabs import surf.xilinx as xil import surf.devices.transceivers as xceiver @@ -132,6 +133,14 @@ def __init__(self, enabled = False, # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline )) + elif (boardType == 'XilinxVariumC1100'): + # self.add(silabs.Si5345( + self.add(silabs.Si5394( + offset = 0x70000, + memBase = self.AxilBridge.proxy, + enabled = False, # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline + )) + def _start(self): super()._start() if not (self.sim) and (self.startArmed): diff --git a/python/axipcie/_TerminateQsfp.py b/python/axipcie/_TerminateQsfp.py new file mode 100644 index 00000000..56144131 --- /dev/null +++ b/python/axipcie/_TerminateQsfp.py @@ -0,0 +1,27 @@ +#----------------------------------------------------------------------------- +# This file is part of the 'axi-pcie-core'. It is subject to +# the license terms in the LICENSE.txt file found in the top-level directory +# of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of the 'axi-pcie-core', including this file, may be +# copied, modified, propagated, or distributed except according to the terms +# contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- + +import pyrogue as pr + +class TerminateQsfp(pr.Device): + def __init__(self,numRefClk=4,**kwargs): + super().__init__(**kwargs) + + self.addRemoteVariables( + name = 'RefClkFreq', + offset = 0x0, + bitSize = 32, + mode = 'RO', + number = numRefClk, + stride = 4, + disp = '{:d}', + units = 'Hz', + pollInterval = 1, + ) diff --git a/python/axipcie/__init__.py b/python/axipcie/__init__.py index e3d28f99..4b4a6960 100644 --- a/python/axipcie/__init__.py +++ b/python/axipcie/__init__.py @@ -7,9 +7,10 @@ # copied, modified, propagated, or distributed except according to the terms # contained in the LICENSE.txt file. #----------------------------------------------------------------------------- -from axipcie._AxiGpuAsyncCore import * -from axipcie._AxiPcieCore import * -from axipcie._AxiPcieDma import * -from axipcie._AxiPcieRoot import * -from axipcie._AxiPipCore import * -from axipcie._PcieAxiVersion import * +from axipcie._AxiGpuAsyncCore import * +from axipcie._AxiPcieCore import * +from axipcie._AxiPcieDma import * +from axipcie._AxiPcieRoot import * +from axipcie._AxiPipCore import * +from axipcie._PcieAxiVersion import * +from axipcie._TerminateQsfp import * From 8f9e0a5291ccfe73beebc77d2747ccf568422665 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 15 Mar 2022 11:41:58 -0700 Subject: [PATCH 2/5] backing up progress --- .../Si5394_GTY_REFCLK_156p25MHz.csv | 24 +++++++++---------- .../Si5394_GTY_REFCLK_156p25MHz.mem | 2 +- .../Si5394_GTY_REFCLK_156p25MHz.slabtimeproj | 4 ++-- .../pcie-3x16/rtl/XilinxAlveoU55cCore.vhd | 2 +- hardware/XilinxAlveoU55c/pcie-3x16/ruckus.tcl | 1 + .../pcie-3x16/xdc/XilinxAlveoU55cTiming.xdc | 13 ++++++++++ .../xdc/XilinxAlveoU55cApp.xdc | 3 ++- .../xdc/XilinxAlveoU55cCore.xdc | 4 ---- .../pcie-3x16/rtl/XilinxVariumC1100Core.vhd | 2 +- .../XilinxVariumC1100/pcie-3x16/ruckus.tcl | 1 + .../pcie-3x16/xdc/XilinxVariumC1100Timing.xdc | 13 ++++++++++ 11 files changed, 47 insertions(+), 22 deletions(-) create mode 100644 hardware/XilinxAlveoU55c/pcie-3x16/xdc/XilinxAlveoU55cTiming.xdc create mode 100644 hardware/XilinxVariumC1100/pcie-3x16/xdc/XilinxVariumC1100Timing.xdc diff --git a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv index 5d6eeeb1..a4f29cc7 100644 --- a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv +++ b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv @@ -4,7 +4,7 @@ Address,Data 0x0008,0x00 0x000B,0x68 0x0016,0x02 -0x0017,0xDC +0x0017,0xFC 0x0018,0xFF 0x0019,0xFF 0x001A,0xFF @@ -92,14 +92,14 @@ Address,Data 0x00EC,0x00 0x00ED,0x00 0x0102,0x01 -0x0112,0x02 +0x0112,0x06 0x0113,0x09 0x0114,0x3B -0x0115,0x29 -0x0117,0x02 +0x0115,0x28 +0x0117,0x06 0x0118,0x09 0x0119,0x3B -0x011A,0x29 +0x011A,0x28 0x0126,0x06 0x0127,0x09 0x0128,0x3B @@ -167,10 +167,10 @@ Address,Data 0x023C,0x00 0x023D,0x00 0x023E,0x80 -0x0250,0x01 +0x0250,0x00 0x0251,0x00 0x0252,0x00 -0x0253,0x01 +0x0253,0x00 0x0254,0x00 0x0255,0x00 0x025C,0x00 @@ -224,12 +224,12 @@ Address,Data 0x030E,0x00 0x030F,0x00 0x0310,0x00 -0x0311,0x10 +0x0311,0x00 0x0312,0x00 0x0313,0x00 0x0314,0x00 0x0315,0x00 -0x0316,0xC8 +0x0316,0x00 0x0317,0x00 0x0318,0x00 0x0319,0x00 @@ -455,9 +455,9 @@ Address,Data 0x094F,0xF2 0x095E,0x00 0x0A02,0x00 -0x0A03,0x03 +0x0A03,0x01 0x0A04,0x01 -0x0A05,0x03 +0x0A05,0x01 0x0A14,0x00 0x0A1A,0x00 0x0A20,0x00 @@ -494,7 +494,7 @@ Address,Data 0x0B46,0x00 0x0B47,0x0F 0x0B48,0x0F -0x0B4A,0x0C +0x0B4A,0x0E 0x0B57,0x0E 0x0B58,0x01 0x0C02,0x03 diff --git a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem index 58e07261..ce2c7d14 100644 --- a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem +++ b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7f5f2b4506bfd2520601b91405b3114829ccacbc81379419ccff72dfa76c7178 +oid sha256:73683f3c7519368ede3c1c6fddfc0dce3a343c255badd172792b9dc70c8e762e size 7168 diff --git a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj index d8426dad..669b07ac 100644 --- a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj +++ b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:96d232cfb276219ce09338f00ac08080b665ca3ce1421973efce4ab040852c88 -size 11304 +oid sha256:b7479b2a969074b6caa56b8bfb7b95b46eb62fb6ad28c7fbbf94b34e5b67de36 +size 11352 diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd b/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd index 079aa4be..26f72133 100644 --- a/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd +++ b/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd @@ -206,7 +206,7 @@ begin TPD_G => TPD_G, MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G, I2C_BASE_ADDR_G => "00", - I2C_SCL_FREQ_G => 100.0E+3, -- units of Hz + I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz AXIL_CLK_FREQ_G => DMA_CLK_FREQ_C) -- units of Hz port map ( -- I2C Ports diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/ruckus.tcl b/hardware/XilinxAlveoU55c/pcie-3x16/ruckus.tcl index cee9c84d..056b7513 100644 --- a/hardware/XilinxAlveoU55c/pcie-3x16/ruckus.tcl +++ b/hardware/XilinxAlveoU55c/pcie-3x16/ruckus.tcl @@ -3,6 +3,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load local Source Code and Constraints loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl" +loadConstraints -dir "$::DIR_PATH/xdc" # loadIpCore -path "$::DIR_PATH/ip/XilinxAlveoU55cPciePhyGen3x16.xci" diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/xdc/XilinxAlveoU55cTiming.xdc b/hardware/XilinxAlveoU55c/pcie-3x16/xdc/XilinxAlveoU55cTiming.xdc new file mode 100644 index 00000000..34cfc547 --- /dev/null +++ b/hardware/XilinxAlveoU55c/pcie-3x16/xdc/XilinxAlveoU55cTiming.xdc @@ -0,0 +1,13 @@ +############################################################################## +## This file is part of 'axi-pcie-core'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'axi-pcie-core', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxAlveoU55cPciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks dnaClk] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxAlveoU55cPciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks iprogClk] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxAlveoU55cPciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks -of_objects [get_pins U_axilClk/PllGen.U_Pll/CLKOUT0] diff --git a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc index 217af029..8afd7b84 100644 --- a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc +++ b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc @@ -73,8 +73,9 @@ set_property PACKAGE_PIN V52 [get_ports { qsfp1RxN[3] }] create_clock -period 6.4 -name qsfp0RefClkP [get_ports {qsfp0RefClkP}] ;# 156.25 MHz (after reprogramming Si5394) create_clock -period 6.4 -name qsfp1RefClkP [get_ports {qsfp1RefClkP}] ;# 156.25 MHz (after reprogramming Si5394) -set_clock_groups -asynchronous +set_clock_groups -asynchronous \ -group [get_clocks -include_generated_clocks {qsfp0RefClkP}] \ -group [get_clocks -include_generated_clocks {qsfp1RefClkP}] \ -group [get_clocks -include_generated_clocks {pciRefClk0}] \ + -group [get_clocks -include_generated_clocks {pciRefClk1}] \ -group [get_clocks -include_generated_clocks {userClkP}] diff --git a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc index 1e0cdbd7..568a6669 100644 --- a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc +++ b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc @@ -133,10 +133,6 @@ create_clock -period 16.000 -name iprogClk [get_pins {U_Core/U_REG/U_Version/ set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClk0}] -group [get_clocks -include_generated_clocks {userClkP}] set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClk1}] -group [get_clocks -include_generated_clocks {userClkP}] -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxAlveoU55cPciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks dnaClk] -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxAlveoU55cPciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks iprogClk] -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxAlveoU55cPciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks -of_objects [get_pins U_axilClk/PllGen.U_Pll/CLKOUT0] - set_false_path -to [get_pins -hier *sync_reg[0]/D] set_false_path -from [get_ports {pciRstL}] diff --git a/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd b/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd index c118e72d..47b56b16 100644 --- a/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd +++ b/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd @@ -206,7 +206,7 @@ begin TPD_G => TPD_G, MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G, I2C_BASE_ADDR_G => "00", - I2C_SCL_FREQ_G => 100.0E+3, -- units of Hz + I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz AXIL_CLK_FREQ_G => DMA_CLK_FREQ_C) -- units of Hz port map ( -- I2C Ports diff --git a/hardware/XilinxVariumC1100/pcie-3x16/ruckus.tcl b/hardware/XilinxVariumC1100/pcie-3x16/ruckus.tcl index 6fe55bbe..aa994872 100644 --- a/hardware/XilinxVariumC1100/pcie-3x16/ruckus.tcl +++ b/hardware/XilinxVariumC1100/pcie-3x16/ruckus.tcl @@ -3,6 +3,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load local Source Code and Constraints loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl" +loadConstraints -dir "$::DIR_PATH/xdc" # loadIpCore -path "$::DIR_PATH/ip/XilinxVariumC1100PciePhyGen3x16.xci" diff --git a/hardware/XilinxVariumC1100/pcie-3x16/xdc/XilinxVariumC1100Timing.xdc b/hardware/XilinxVariumC1100/pcie-3x16/xdc/XilinxVariumC1100Timing.xdc new file mode 100644 index 00000000..cb70e08b --- /dev/null +++ b/hardware/XilinxVariumC1100/pcie-3x16/xdc/XilinxVariumC1100Timing.xdc @@ -0,0 +1,13 @@ +############################################################################## +## This file is part of 'axi-pcie-core'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'axi-pcie-core', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks dnaClk] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks iprogClk] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxVariumC1100PciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks -of_objects [get_pins U_axilClk/PllGen.U_Pll/CLKOUT0] From 9e924157fa61b63d7107f3fccf454406e6551f45 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 15 Mar 2022 17:06:55 -0700 Subject: [PATCH 3/5] updating boot up clock configuration --- .../Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv | 8 ++++---- .../Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem | 2 +- .../Si5394_GTY_REFCLK_156p25MHz.slabtimeproj | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv index a4f29cc7..8a2d61ea 100644 --- a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv +++ b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv @@ -160,13 +160,13 @@ Address,Data 0x0235,0x00 0x0236,0x00 0x0237,0x00 -0x0238,0x80 -0x0239,0x89 +0x0238,0xD8 +0x0239,0xD6 0x023A,0x00 0x023B,0x00 0x023C,0x00 0x023D,0x00 -0x023E,0x80 +0x023E,0xC0 0x0250,0x00 0x0251,0x00 0x0252,0x00 @@ -213,7 +213,7 @@ Address,Data 0x0303,0x00 0x0304,0x00 0x0305,0x00 -0x0306,0x21 +0x0306,0x16 0x0307,0x00 0x0308,0x00 0x0309,0x00 diff --git a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem index ce2c7d14..273d7a28 100644 --- a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem +++ b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:73683f3c7519368ede3c1c6fddfc0dce3a343c255badd172792b9dc70c8e762e +oid sha256:5f8b0961e8d8b58815600ff9f76c247edd626c35f8502b0038688b78a3705702 size 7168 diff --git a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj index 669b07ac..05330fa0 100644 --- a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj +++ b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b7479b2a969074b6caa56b8bfb7b95b46eb62fb6ad28c7fbbf94b34e5b67de36 -size 11352 +oid sha256:4a3219d6483bc59b9060033d4142539daa70c64ce66b37faa991ff8d893def41 +size 11368 From eee8b67fb1409a9e256854e05067f9bc0fe9c281 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 16 Mar 2022 11:04:35 -0700 Subject: [PATCH 4/5] adding HBM clock to the core --- .../Si5394_GTY_REFCLK_156p25MHz.csv | 503 ------------------ .../Si5394_GTY_REFCLK_156p25MHz.mem | 3 - .../Si5394_GTY_REFCLK_156p25MHz.slabtimeproj | 3 - .../pcie-3x16/rtl/XilinxAlveoU55cCore.vhd | 65 ++- hardware/XilinxAlveoU55c/ruckus.tcl | 3 - .../xdc/XilinxAlveoU55cApp.xdc | 12 +- .../xdc/XilinxAlveoU55cCore.xdc | 6 +- .../pcie-3x16/rtl/XilinxVariumC1100Core.vhd | 17 +- hardware/XilinxVariumC1100/ruckus.tcl | 3 - python/axipcie/_AxiPcieCore.py | 3 +- 10 files changed, 62 insertions(+), 556 deletions(-) delete mode 100644 hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv delete mode 100644 hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem delete mode 100644 hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj diff --git a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv deleted file mode 100644 index 8a2d61ea..00000000 --- a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.csv +++ /dev/null @@ -1,503 +0,0 @@ -Address,Data -0x0006,0x00 -0x0007,0x00 -0x0008,0x00 -0x000B,0x68 -0x0016,0x02 -0x0017,0xFC -0x0018,0xFF -0x0019,0xFF -0x001A,0xFF -0x002B,0x0A -0x002C,0x00 -0x002D,0x00 -0x002E,0x00 -0x002F,0x00 -0x0030,0x00 -0x0031,0x00 -0x0032,0x00 -0x0033,0x00 -0x0034,0x00 -0x0035,0x00 -0x0036,0x00 -0x0037,0x00 -0x0038,0x00 -0x0039,0x00 -0x003A,0x00 -0x003B,0x00 -0x003C,0x00 -0x003D,0x00 -0x003E,0x00 -0x003F,0x00 -0x0040,0x04 -0x0041,0x00 -0x0042,0x00 -0x0043,0x00 -0x0044,0x00 -0x0045,0x0C -0x0046,0x00 -0x0047,0x00 -0x0048,0x00 -0x0049,0x00 -0x004A,0x00 -0x004B,0x00 -0x004C,0x00 -0x004D,0x00 -0x004E,0x00 -0x004F,0x00 -0x0050,0x0F -0x0051,0x00 -0x0052,0x00 -0x0053,0x00 -0x0054,0x00 -0x0055,0x00 -0x0056,0x00 -0x0057,0x00 -0x0058,0x00 -0x0059,0x00 -0x005A,0x00 -0x005B,0x00 -0x005C,0x00 -0x005D,0x00 -0x005E,0x00 -0x005F,0x00 -0x0060,0x00 -0x0061,0x00 -0x0062,0x00 -0x0063,0x00 -0x0064,0x00 -0x0065,0x00 -0x0066,0x00 -0x0067,0x00 -0x0068,0x00 -0x0069,0x00 -0x0092,0x00 -0x0093,0x00 -0x0095,0x00 -0x0096,0x00 -0x0098,0x00 -0x009A,0x00 -0x009B,0x00 -0x009D,0x00 -0x009E,0x00 -0x00A0,0x00 -0x00A2,0x00 -0x00A9,0x00 -0x00AA,0x00 -0x00AB,0x00 -0x00AC,0x00 -0x00E5,0x01 -0x00EA,0x00 -0x00EB,0x00 -0x00EC,0x00 -0x00ED,0x00 -0x0102,0x01 -0x0112,0x06 -0x0113,0x09 -0x0114,0x3B -0x0115,0x28 -0x0117,0x06 -0x0118,0x09 -0x0119,0x3B -0x011A,0x28 -0x0126,0x06 -0x0127,0x09 -0x0128,0x3B -0x0129,0x28 -0x012B,0x06 -0x012C,0x09 -0x012D,0x3B -0x012E,0x28 -0x013F,0x00 -0x0140,0x00 -0x0141,0x40 -0x0142,0xFF -0x0206,0x00 -0x0208,0x00 -0x0209,0x00 -0x020A,0x00 -0x020B,0x00 -0x020C,0x00 -0x020D,0x00 -0x020E,0x00 -0x020F,0x00 -0x0210,0x00 -0x0211,0x00 -0x0212,0x00 -0x0213,0x00 -0x0214,0x00 -0x0215,0x00 -0x0216,0x00 -0x0217,0x00 -0x0218,0x00 -0x0219,0x00 -0x021A,0x00 -0x021B,0x00 -0x021C,0x00 -0x021D,0x00 -0x021E,0x00 -0x021F,0x00 -0x0220,0x00 -0x0221,0x00 -0x0222,0x00 -0x0223,0x00 -0x0224,0x00 -0x0225,0x00 -0x0226,0x00 -0x0227,0x00 -0x0228,0x00 -0x0229,0x00 -0x022A,0x00 -0x022B,0x00 -0x022C,0x00 -0x022D,0x00 -0x022E,0x00 -0x022F,0x00 -0x0231,0x0B -0x0232,0x0B -0x0233,0x0B -0x0234,0x0B -0x0235,0x00 -0x0236,0x00 -0x0237,0x00 -0x0238,0xD8 -0x0239,0xD6 -0x023A,0x00 -0x023B,0x00 -0x023C,0x00 -0x023D,0x00 -0x023E,0xC0 -0x0250,0x00 -0x0251,0x00 -0x0252,0x00 -0x0253,0x00 -0x0254,0x00 -0x0255,0x00 -0x025C,0x00 -0x025D,0x00 -0x025E,0x00 -0x025F,0x00 -0x0260,0x00 -0x0261,0x00 -0x026B,0x00 -0x026C,0x00 -0x026D,0x00 -0x026E,0x00 -0x026F,0x00 -0x0270,0x00 -0x0271,0x00 -0x0272,0x00 -0x028A,0x00 -0x028B,0x00 -0x028C,0x00 -0x028D,0x00 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-0x0849,0x00 -0x084A,0x00 -0x084B,0x00 -0x084C,0x00 -0x084D,0x00 -0x084E,0x00 -0x084F,0x00 -0x0850,0x00 -0x0851,0x00 -0x0852,0x00 -0x0853,0x00 -0x0854,0x00 -0x0855,0x00 -0x0856,0x00 -0x0857,0x00 -0x0858,0x00 -0x0859,0x00 -0x085A,0x00 -0x085B,0x00 -0x085C,0x00 -0x085D,0x00 -0x085E,0x00 -0x085F,0x00 -0x0860,0x00 -0x0861,0x00 -0x090E,0x02 -0x0943,0x00 -0x0949,0x00 -0x094A,0x00 -0x094E,0x49 -0x094F,0xF2 -0x095E,0x00 -0x0A02,0x00 -0x0A03,0x01 -0x0A04,0x01 -0x0A05,0x01 -0x0A14,0x00 -0x0A1A,0x00 -0x0A20,0x00 -0x0A26,0x00 -0x0A38,0x00 -0x0A39,0x00 -0x0A3A,0x00 -0x0A3C,0x00 -0x0A3D,0x00 -0x0A3E,0x00 -0x0A40,0x00 -0x0A41,0x00 -0x0A42,0x00 -0x0A44,0x00 -0x0A45,0x00 -0x0A46,0x00 -0x0A4C,0x00 -0x0A4D,0x00 -0x0A4E,0x00 -0x0A4F,0x00 -0x0A50,0x00 -0x0A51,0x00 -0x0A52,0x00 -0x0A53,0x00 -0x0A54,0x00 -0x0A55,0x00 -0x0A56,0x00 -0x0A57,0x00 -0x0A58,0x00 -0x0A59,0x00 -0x0A5A,0x00 -0x0A5B,0x00 -0x0B44,0x0F -0x0B46,0x00 -0x0B47,0x0F -0x0B48,0x0F -0x0B4A,0x0E -0x0B57,0x0E -0x0B58,0x01 -0x0C02,0x03 -0x0C03,0x00 -0x0C07,0x00 -0x0C08,0x00 diff --git a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem deleted file mode 100644 index 273d7a28..00000000 --- a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:5f8b0961e8d8b58815600ff9f76c247edd626c35f8502b0038688b78a3705702 -size 7168 diff --git a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj b/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj deleted file mode 100644 index 05330fa0..00000000 --- a/hardware/XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.slabtimeproj +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:4a3219d6483bc59b9060033d4142539daa70c64ce66b37faa991ff8d893def41 -size 11368 diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd b/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd index 26f72133..11cdbf87 100644 --- a/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd +++ b/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd @@ -34,7 +34,7 @@ use unisim.vcomponents.all; entity XilinxAlveoU55cCore is generic ( TPD_G : time := 1 ns; - SI5394_INIT_FILE_G : string := "Si5394_GTY_REFCLK_156p25MHz.mem"; + SI5394_INIT_FILE_G : string := "none"; ROGUE_SIM_EN_G : boolean := false; ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000; ROGUE_SIM_CH_COUNT_G : natural range 1 to 256 := 256; @@ -47,33 +47,36 @@ entity XilinxAlveoU55cCore is ------------------------ -- Top Level Interfaces ------------------------ - userClk100 : out sl; + userClk : out sl; + hbmRefClk : out sl; -- DMA Interfaces (dmaClk domain) - dmaClk : out sl; - dmaRst : out sl; - dmaBuffGrpPause : out slv(7 downto 0); - dmaObMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); - dmaObSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); - dmaIbMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); - dmaIbSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + dmaClk : out sl; + dmaRst : out sl; + dmaBuffGrpPause : out slv(7 downto 0); + dmaObMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + dmaObSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + dmaIbMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + dmaIbSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); -- PIP Interface [0x00080000:0009FFFF] (dmaClk domain) - pipIbMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - pipIbSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; - pipObMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - pipObSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; + pipIbMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + pipIbSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; + pipObMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + pipObSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; -- Application AXI-Lite Interfaces [0x00100000:0x00FFFFFF] (appClk domain) - appClk : in sl := '0'; - appRst : in sl := '1'; - appReadMaster : out AxiLiteReadMasterType; - appReadSlave : in AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C; - appWriteMaster : out AxiLiteWriteMasterType; - appWriteSlave : in AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C; + appClk : in sl := '0'; + appRst : in sl := '1'; + appReadMaster : out AxiLiteReadMasterType; + appReadSlave : in AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C; + appWriteMaster : out AxiLiteWriteMasterType; + appWriteSlave : in AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C; ------------------- -- Top Level Ports ------------------- -- System Ports userClkP : in sl; userClkN : in sl; + hbmRefClkP : in sl; + hbmRefClkN : in sl; -- SI5394 Ports si5394Scl : inout sl; si5394Sda : inout sl; @@ -82,13 +85,13 @@ entity XilinxAlveoU55cCore is si5394LosL : in sl; si5394RstL : out sl; -- PCIe Ports - pciRstL : in sl; - pciRefClkP : in slv(1 downto 0); - pciRefClkN : in slv(1 downto 0); - pciRxP : in slv(15 downto 0); - pciRxN : in slv(15 downto 0); - pciTxP : out slv(15 downto 0); - pciTxN : out slv(15 downto 0)); + pciRstL : in sl; + pciRefClkP : in slv(1 downto 0); + pciRefClkN : in slv(1 downto 0); + pciRxP : in slv(15 downto 0); + pciRxN : in slv(15 downto 0); + pciTxP : out slv(15 downto 0); + pciTxN : out slv(15 downto 0)); end XilinxAlveoU55cCore; architecture mapping of XilinxAlveoU55cCore is @@ -154,11 +157,17 @@ begin systemReset <= sysReset or cardReset; systemResetL <= not(systemReset); - U_IBUFDS : IBUFDS + U_userClk : IBUFDS port map( I => userClkP, IB => userClkN, - O => userClk100); + O => userClk); + + U_hbmRefClk : IBUFDS + port map( + I => hbmRefClkP, + IB => hbmRefClkN, + O => hbmRefClk); --------------- -- AXI PCIe PHY diff --git a/hardware/XilinxAlveoU55c/ruckus.tcl b/hardware/XilinxAlveoU55c/ruckus.tcl index 3fc16279..5289864e 100644 --- a/hardware/XilinxAlveoU55c/ruckus.tcl +++ b/hardware/XilinxAlveoU55c/ruckus.tcl @@ -33,6 +33,3 @@ loadConstraints -path "$::DIR_PATH/xdc/XilinxAlveoU55cApp.xdc" # Load the PCIe core loadRuckusTcl "$::DIR_PATH/${pcieType}" - -# Adding the common Si5345 configuration -add_files -norecurse "$::DIR_PATH/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem" diff --git a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc index 8afd7b84..49f8f726 100644 --- a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc +++ b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc @@ -15,8 +15,8 @@ set_property -dict { PACKAGE_PIN BE45 IOSTANDARD LVCMOS18 PULLDOWN TRUE } [get_p # QSFP[0] - QSFP28 MGTY Interface QUAD 130 ########################################## -set_property PACKAGE_PIN AD42 [get_ports { qsfp0RefClkP }] ;# MGTREFCLK0P_130: 156.25 MHz (after reprogramming Si5394) -set_property PACKAGE_PIN AD43 [get_ports { qsfp0RefClkN }] ;# MGTREFCLK0N_130: 156.25 MHz (after reprogramming Si5394) +set_property PACKAGE_PIN AD42 [get_ports { qsfp0RefClkP }] +set_property PACKAGE_PIN AD43 [get_ports { qsfp0RefClkN }] set_property PACKAGE_PIN AD46 [get_ports { qsfp0TxP[0] }] set_property PACKAGE_PIN AD47 [get_ports { qsfp0TxN[0] }] @@ -42,8 +42,8 @@ set_property PACKAGE_PIN AB52 [get_ports { qsfp0RxN[3] }] # QSFP[0] - QSFP28 MGTY Interface QUAD 131 ########################################## -set_property PACKAGE_PIN AB42 [get_ports { qsfp1RefClkP }] ;# MGTREFCLK0P_131: 156.25 MHz (after reprogramming Si5394) -set_property PACKAGE_PIN AB43 [get_ports { qsfp1RefClkN }] ;# MGTREFCLK0N_131: 156.25 MHz (after reprogramming Si5394) +set_property PACKAGE_PIN AB42 [get_ports { qsfp1RefClkP }] +set_property PACKAGE_PIN AB43 [get_ports { qsfp1RefClkN }] set_property PACKAGE_PIN AA44 [get_ports { qsfp1TxP[0] }] set_property PACKAGE_PIN AA45 [get_ports { qsfp1TxN[0] }] @@ -70,8 +70,8 @@ set_property PACKAGE_PIN V52 [get_ports { qsfp1RxN[3] }] # Clocks # ########## -create_clock -period 6.4 -name qsfp0RefClkP [get_ports {qsfp0RefClkP}] ;# 156.25 MHz (after reprogramming Si5394) -create_clock -period 6.4 -name qsfp1RefClkP [get_ports {qsfp1RefClkP}] ;# 156.25 MHz (after reprogramming Si5394) +create_clock -period 6.206 -name qsfp0RefClkP [get_ports {qsfp0RefClkP}] ;# 161.1328125 MHz +create_clock -period 6.206 -name qsfp1RefClkP [get_ports {qsfp1RefClkP}] ;# 161.1328125 MHz set_clock_groups -asynchronous \ -group [get_clocks -include_generated_clocks {qsfp0RefClkP}] \ diff --git a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc index 568a6669..38eb4d1a 100644 --- a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc +++ b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc @@ -8,7 +8,7 @@ ## the terms contained in the LICENSE.txt file. ############################################################################## -# set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_Core}] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_Core}] set_operating_conditions -design_power_budget 63 @@ -19,6 +19,9 @@ set_operating_conditions -design_power_budget 63 set_property -dict { PACKAGE_PIN BK10 IOSTANDARD LVDS } [get_ports { userClkP }] set_property -dict { PACKAGE_PIN BL10 IOSTANDARD LVDS } [get_ports { userClkN }] +set_property -dict { PACKAGE_PIN BK43 IOSTANDARD LVDS } [get_ports { hbmRefClkP }] +set_property -dict { PACKAGE_PIN BK44 IOSTANDARD LVDS } [get_ports { hbmRefClkN }] + set_property -dict { PACKAGE_PIN BM14 IOSTANDARD LVCMOS18 } [get_ports { si5394Scl }] set_property -dict { PACKAGE_PIN BN14 IOSTANDARD LVCMOS18 } [get_ports { si5394Sda }] set_property -dict { PACKAGE_PIN BM9 IOSTANDARD LVCMOS18 } [get_ports { si5394IrqL }] @@ -127,6 +130,7 @@ set_property PULLUP true [get_ports pciRstL] create_clock -period 10.000 -name pciRefClk0 [get_ports {pciRefClkP[0]}] create_clock -period 10.000 -name pciRefClk1 [get_ports {pciRefClkP[1]}] create_clock -period 10.000 -name userClkP [get_ports {userClkP}] +create_clock -period 10.000 -name hbmRefClkP [get_ports {hbmRefClkP}] create_clock -period 16.000 -name dnaClk [get_pins {U_Core/U_REG/U_Version/GEN_DEVICE_DNA.DeviceDna_1/GEN_ULTRA_SCALE.DeviceDnaUltraScale_Inst/BUFGCE_DIV_Inst/O}] create_clock -period 16.000 -name iprogClk [get_pins {U_Core/U_REG/U_Version/GEN_ICAP.Iprog_1/GEN_ULTRA_SCALE.IprogUltraScale_Inst/BUFGCE_DIV_Inst/O}] diff --git a/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd b/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd index 47b56b16..e26522ee 100644 --- a/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd +++ b/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd @@ -34,7 +34,7 @@ use unisim.vcomponents.all; entity XilinxVariumC1100Core is generic ( TPD_G : time := 1 ns; - SI5394_INIT_FILE_G : string := "Si5394_GTY_REFCLK_156p25MHz.mem"; + SI5394_INIT_FILE_G : string := "none"; ROGUE_SIM_EN_G : boolean := false; ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000; ROGUE_SIM_CH_COUNT_G : natural range 1 to 256 := 256; @@ -47,7 +47,8 @@ entity XilinxVariumC1100Core is ------------------------ -- Top Level Interfaces ------------------------ - userClk100 : out sl; + userClk : out sl; + hbmRefClk : out sl; -- DMA Interfaces (dmaClk domain) dmaClk : out sl; dmaRst : out sl; @@ -74,6 +75,8 @@ entity XilinxVariumC1100Core is -- System Ports userClkP : in sl; userClkN : in sl; + hbmRefClkP : in sl; + hbmRefClkN : in sl; -- SI5394 Ports si5394Scl : inout sl; si5394Sda : inout sl; @@ -154,11 +157,17 @@ begin systemReset <= sysReset or cardReset; systemResetL <= not(systemReset); - U_IBUFDS : IBUFDS + U_userClk : IBUFDS port map( I => userClkP, IB => userClkN, - O => userClk100); + O => userClk); + + U_hbmRefClk : IBUFDS + port map( + I => hbmRefClkP, + IB => hbmRefClkN, + O => hbmRefClk); --------------- -- AXI PCIe PHY diff --git a/hardware/XilinxVariumC1100/ruckus.tcl b/hardware/XilinxVariumC1100/ruckus.tcl index 1a3df07c..4d813eff 100644 --- a/hardware/XilinxVariumC1100/ruckus.tcl +++ b/hardware/XilinxVariumC1100/ruckus.tcl @@ -33,6 +33,3 @@ loadConstraints -path "$::DIR_PATH/../XilinxAlveoU55c/xdc/XilinxAl # Load the PCIe core loadRuckusTcl "$::DIR_PATH/${pcieType}" - -# Adding the common Si5345 configuration -add_files -norecurse "$::DIR_PATH/../XilinxAlveoU55c/Si5394-config/Si5394_GTY_REFCLK_156p25MHz.mem" diff --git a/python/axipcie/_AxiPcieCore.py b/python/axipcie/_AxiPcieCore.py index ce4f05c8..8728b5eb 100644 --- a/python/axipcie/_AxiPcieCore.py +++ b/python/axipcie/_AxiPcieCore.py @@ -133,8 +133,7 @@ def __init__(self, enabled = False, # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline )) - elif (boardType == 'XilinxVariumC1100'): - # self.add(silabs.Si5345( + elif (boardType == 'XilinxAlveoU55c') or (boardType == 'XilinxVariumC1100'): self.add(silabs.Si5394( offset = 0x70000, memBase = self.AxilBridge.proxy, From 522727744b2cc1a97b2c50bb93782bb92a73c4ce Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 16 Mar 2022 16:20:51 -0700 Subject: [PATCH 5/5] updating submodules locks --- shared/ruckus.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/shared/ruckus.tcl b/shared/ruckus.tcl index 0c39bec8..d27c38c7 100644 --- a/shared/ruckus.tcl +++ b/shared/ruckus.tcl @@ -3,8 +3,8 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Check for submodule tagging if { [info exists ::env(OVERRIDE_SUBMODULE_LOCKS)] != 1 || $::env(OVERRIDE_SUBMODULE_LOCKS) == 0 } { - if { [SubmoduleCheck {ruckus} {2.6.0} ] < 0 } {exit -1} - if { [SubmoduleCheck {surf} {2.21.0} ] < 0 } {exit -1} + if { [SubmoduleCheck {ruckus} {4.3.2} ] < 0 } {exit -1} + if { [SubmoduleCheck {surf} {2.31.0} ] < 0 } {exit -1} } else { puts "\n\n*********************************************************" puts "OVERRIDE_SUBMODULE_LOCKS != 0"