Coreblocks is an experimental, modular out-of-order RISC-V core generator implemented in Amaranth. Its design goals are:
- Simplicity. Coreblocks is an academic project, accessible to students. It should be suitable for teaching essentials of out-of-order architectures.
- Modularity. We want to be able to easily experiment with the core by adding, replacing and modifying modules without changing the source too much. For this goal, we designed a transaction system inspired by Bluespec.
- Fine-grained testing. Outside of the integration tests for the full core, modules are tested individually. This is to support an agile style of development.
In the future, we would like to achieve the following goals:
- Performace (up to a point, on FPGAs). We would like Coreblocks not to be too sluggish, without compromising the simplicity goal. We don't wish to compete with high performance cores like BOOM though.
- Wide(r) RISC-V support. Currently, we are focusing on getting the support for the core RV32I ISA right, but the ambitious long term plan is to be able to run full operating systems (e.g. Linux) on the core.
The core currently supports the full RV32I instruction set and several extensions, including M (multiplication and division) and C (compressed instructions). Interrupts and exceptions are currently not supported. Coreblocks can be used with LiteX (currently using a patched version).
The transaction system we use as the foundation for the core is well-tested and usable. We plan to make it available as a separate Python package.
The documentation for our project is automatically generated using Sphinx.
Resource usage and maximum clock frequency is automatically measured and recorded.
Set up the development environment following the project documetation.
External contributors are welcome to submit pull requests for simple contributions directly. For larger changes, please discuss your plans with us through the issues page or the discussions page first. This way, you can ensure that the contribution fits the project and will be merged sooner.
Copyright © 2022-2023, University of Wrocław.
This project is three-clause BSD licensed.