joelquev/joelquev is my introduction repository✨✨
I'm a PhD Student working on High-Level Synthesis and Hardware Design, always interested in to hear about projects related to FPGAs, Evolutionary Algorithms and Compilers.
Also, I'm familiar with compiler infrastructures such a LLVM/MLIR and the basics of Linux, TCL and Scripting. I have technical skills in VHDL (Design and Debug using Xilinx Vivado), MATLAB and Python programming. I'm currently exploring UVM for system verification with SystemVerilog.