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Pull requests: llvm/circt

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Pull requests list

[SV] Add MacroRefOp to represet macro statement
#7607 opened Sep 18, 2024 by uenoku Loading…
[Seq] Add a pass to implement firreg randomization
#7606 opened Sep 18, 2024 by uenoku Loading…
Add verif.bmc VerifToSMT lowering
#7603 opened Sep 16, 2024 by TaoBi22 Loading…
21
[Moore] Support the display system task. ImportVerilog Moore
#7600 opened Sep 14, 2024 by hailongSun2000 Loading…
3
[FIRRTL] Add layer block support to AddSeqMemPorts
#7599 opened Sep 14, 2024 by seldridge Loading…
1
[Moore] Add assert, assume, and cover ops. ImportVerilog Moore
#7589 opened Sep 6, 2024 by hailongSun2000 Loading…
12
[Arc][Vectorization]: Add vector splitter
#7560 opened Aug 30, 2024 by elhewaty • Draft
2
[Arc] Implement memory initializers Arc Involving the `arc` dialect
#7559 opened Aug 28, 2024 by fzi-hielscher • Draft
17
[FIRRTL] Verify enabled layers of module, extmodule.
#7557 opened Aug 26, 2024 by dtzSiFive Loading…
4
Advanced LayerSink
#7548 opened Aug 23, 2024 by rwy7 • Draft
2
[FIRRTL] Add layers output file to file list
#7543 opened Aug 22, 2024 by SpriteOvO Loading…
1
2
[CheckCombLoops] Report all the operations that participate in the cycle, when reporting a cycle
#7539 opened Aug 21, 2024 by prithayan • Draft
[OM] Rework ClassOp to use fields terminator
#7537 opened Aug 20, 2024 by leonardt Loading…
34
[firtool] Run canonicalization before LowerLayers
#7534 opened Aug 19, 2024 by seldridge Loading…
1
2
[Comb] Let parent op decide if cross-block canonicalizations should be allowed Comb Involving the `comb` dialect
#7529 opened Aug 19, 2024 by maerhart • Draft
1
Bump LLVM to LLVM 19.1.0-rc1 in release/19.x branch
#7524 opened Aug 16, 2024 by uenoku Loading…
[Seq] Add a new pass to sink clock_gate ops to the users
#7474 opened Aug 8, 2024 by prithayan Loading…
39
[Scheduling] add a header to simplex scheduler
#7466 opened Aug 8, 2024 by leothaud Loading…
17
[Sim] Replace sim.func.dpi.call with sim.func.call and improve a verifier, NFC
#7452 opened Aug 7, 2024 by uenoku Loading…
10
[SCFToCalyx] Lower SCF Parallel Op To Calyx Calyx The Calyx dialect
#7409 opened Jul 30, 2024 by jiahanxie353 • Draft
7
[FIRRTL] Inliner: Support for ops with regions. FIRRTL Involving the `firrtl` dialect
#7398 opened Jul 29, 2024 by dtzSiFive Loading…
16
[ImportVerilog] Add HierarchicalNames.cpp to support hierarchical names. ImportVerilog
#7382 opened Jul 24, 2024 by hailongSun2000 Loading…
13
[firtool] fix: check uninferred resets after removing unused modules
#7380 opened Jul 23, 2024 by unlsycn Loading…
18
[Moore] [Canonicalizer] Lower struct-related assignOp Moore
#7341 opened Jul 18, 2024 by mingzheTerapines Loading…
22
[HW][SV] Transition "HWToSV" to "ProceduralCoreToSV" pass. HW Involving the `hw` dialect Verilog/SystemVerilog Involving a Verilog dialect
#7335 opened Jul 17, 2024 by fzi-hielscher Loading…
8
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