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Merge pull request #88 from slaclab/pre-release
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Release Candidate v3.10.1
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@ruck314
ruck314 committed Mar 16, 2022
2 parents a249ff9 + 6fc1da6 commit 899533d
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19 changes: 16 additions & 3 deletions .gitattributes
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*.dcp filter=lfs diff=lfs merge=lfs -text
*.elf filter=lfs diff=lfs merge=lfs -text
*.bit filter=lfs diff=lfs merge=lfs -text
*.mcs filter=lfs diff=lfs merge=lfs -text
*.gz filter=lfs diff=lfs merge=lfs -text
*.mcs filter=lfs diff=lfs merge=lfs -text
*.bin filter=lfs diff=lfs merge=lfs -text
*.bit filter=lfs diff=lfs merge=lfs -text
*.hdf filter=lfs diff=lfs merge=lfs -text
*.zip filter=lfs diff=lfs merge=lfs -text
*.ZIP filter=lfs diff=lfs merge=lfs -text
*.dat filter=lfs diff=lfs merge=lfs -text
*.hex filter=lfs diff=lfs merge=lfs -text
*.mem filter=lfs diff=lfs merge=lfs -text
*.pdi filter=lfs diff=lfs merge=lfs -text
*.bif filter=lfs diff=lfs merge=lfs -text
*.elf filter=lfs diff=lfs merge=lfs -text
*.slx filter=lfs diff=lfs merge=lfs -text
*.slabtimeproj filter=lfs diff=lfs merge=lfs -text
*.pptx filter=lfs diff=lfs merge=lfs -text
*.xlsx filter=lfs diff=lfs merge=lfs -text
48 changes: 24 additions & 24 deletions hardware/XilinxAlveoU55c/misc/TerminateQsfp.vhd
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Expand Up @@ -71,7 +71,7 @@ architecture mapping of TerminateQsfp is
signal rin : RegType;

signal unusedGtClk : slv(1 downto 0);
signal refClk : slv(1 downto 0);
signal refClk : slv(3 downto 0);
signal refClkBufg : slv(3 downto 0);
signal refClkFreq : Slv32Array(3 downto 0);

Expand Down Expand Up @@ -105,30 +105,30 @@ begin
gtTxN => qsfp1TxN);


U_unusedGtClk0 : IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O
REFCLK_ICNTL_RX => "00")
port map (
I => qsfp0RefClkP,
IB => qsfp0RefClkN,
CEB => '0',
ODIV2 => refClk(0),
O => unusedGtClk(0));

U_unusedGtClk1 : IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O
REFCLK_ICNTL_RX => "00")
port map (
I => qsfp1RefClkP,
IB => qsfp1RefClkN,
CEB => '0',
ODIV2 => refClk(1),
O => unusedGtClk(1));

U_unusedGtClk0 : IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O
REFCLK_ICNTL_RX => "00")
port map (
I => qsfp0RefClkP,
IB => qsfp0RefClkN,
CEB => '0',
ODIV2 => refClk(0),
O => unusedGtClk(0));

U_unusedGtClk1 : IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O
REFCLK_ICNTL_RX => "00")
port map (
I => qsfp1RefClkP,
IB => qsfp1RefClkN,
CEB => '0',
ODIV2 => refClk(1),
O => unusedGtClk(1));

GEN_FREQ_MON : for i in 1 downto 0 generate

Expand Down
110 changes: 81 additions & 29 deletions hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd
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Expand Up @@ -34,6 +34,7 @@ use unisim.vcomponents.all;
entity XilinxAlveoU55cCore is
generic (
TPD_G : time := 1 ns;
SI5394_INIT_FILE_G : string := "none";
ROGUE_SIM_EN_G : boolean := false;
ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000;
ROGUE_SIM_CH_COUNT_G : natural range 1 to 256 := 256;
Expand All @@ -46,41 +47,51 @@ entity XilinxAlveoU55cCore is
------------------------
-- Top Level Interfaces
------------------------
userClk100 : out sl;
userClk : out sl;
hbmRefClk : out sl;
-- DMA Interfaces (dmaClk domain)
dmaClk : out sl;
dmaRst : out sl;
dmaBuffGrpPause : out slv(7 downto 0);
dmaObMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0);
dmaObSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0);
dmaIbMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0);
dmaIbSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0);
dmaClk : out sl;
dmaRst : out sl;
dmaBuffGrpPause : out slv(7 downto 0);
dmaObMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0);
dmaObSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0);
dmaIbMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0);
dmaIbSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0);
-- PIP Interface [0x00080000:0009FFFF] (dmaClk domain)
pipIbMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
pipIbSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C;
pipObMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
pipObSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C;
pipIbMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
pipIbSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C;
pipObMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
pipObSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C;
-- Application AXI-Lite Interfaces [0x00100000:0x00FFFFFF] (appClk domain)
appClk : in sl := '0';
appRst : in sl := '1';
appReadMaster : out AxiLiteReadMasterType;
appReadSlave : in AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C;
appWriteMaster : out AxiLiteWriteMasterType;
appWriteSlave : in AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C;
appClk : in sl := '0';
appRst : in sl := '1';
appReadMaster : out AxiLiteReadMasterType;
appReadSlave : in AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C;
appWriteMaster : out AxiLiteWriteMasterType;
appWriteSlave : in AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C;
-------------------
-- Top Level Ports
-------------------
-- System Ports
userClkP : in sl;
userClkN : in sl;
userClkP : in sl;
userClkN : in sl;
hbmRefClkP : in sl;
hbmRefClkN : in sl;
-- SI5394 Ports
si5394Scl : inout sl;
si5394Sda : inout sl;
si5394IrqL : in sl;
si5394LolL : in sl;
si5394LosL : in sl;
si5394RstL : out sl;
-- PCIe Ports
pciRstL : in sl;
pciRefClkP : in slv(1 downto 0);
pciRefClkN : in slv(1 downto 0);
pciRxP : in slv(15 downto 0);
pciRxN : in slv(15 downto 0);
pciTxP : out slv(15 downto 0);
pciTxN : out slv(15 downto 0));
pciRstL : in sl;
pciRefClkP : in slv(1 downto 0);
pciRefClkN : in slv(1 downto 0);
pciRxP : in slv(15 downto 0);
pciRxN : in slv(15 downto 0);
pciTxP : out slv(15 downto 0);
pciTxN : out slv(15 downto 0));
end XilinxAlveoU55cCore;

architecture mapping of XilinxAlveoU55cCore is
Expand All @@ -105,6 +116,11 @@ architecture mapping of XilinxAlveoU55cCore is
signal phyWriteMaster : AxiLiteWriteMasterType;
signal phyWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C;

signal i2cReadMaster : AxiLiteReadMasterType;
signal i2cReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C;
signal i2cWriteMaster : AxiLiteWriteMasterType;
signal i2cWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C;

signal intPipIbMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
signal intPipIbSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C;
signal intPipObMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
Expand Down Expand Up @@ -141,11 +157,17 @@ begin
systemReset <= sysReset or cardReset;
systemResetL <= not(systemReset);

U_IBUFDS : IBUFDS
U_userClk : IBUFDS
port map(
I => userClkP,
IB => userClkN,
O => userClk100);
O => userClk);

U_hbmRefClk : IBUFDS
port map(
I => hbmRefClkP,
IB => hbmRefClkN,
O => hbmRefClk);

---------------
-- AXI PCIe PHY
Expand Down Expand Up @@ -188,6 +210,31 @@ begin
pipIbMaster <= intPipIbMaster;
intPipIbSlave <= pipIbSlave;

U_SI5394 : entity surf.Si5394I2c
generic map (
TPD_G => TPD_G,
MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G,
I2C_BASE_ADDR_G => "00",
I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz
AXIL_CLK_FREQ_G => DMA_CLK_FREQ_C) -- units of Hz
port map (
-- I2C Ports
scl => si5394Scl,
sda => si5394Sda,
-- Misc Interface
irqL => si5394IrqL,
lolL => si5394LolL,
losL => si5394LosL,
rstL => si5394RstL,
-- AXI-Lite Register Interface
axilReadMaster => i2cReadMaster,
axilReadSlave => i2cReadSlave,
axilWriteMaster => i2cWriteMaster,
axilWriteSlave => i2cWriteSlave,
-- Clocks and Resets
axilClk => sysClock,
axilRst => sysReset);

end generate;

SIM_PCIE : if (ROGUE_SIM_EN_G) generate
Expand Down Expand Up @@ -243,6 +290,11 @@ begin
phyReadSlave => phyReadSlave,
phyWriteMaster => phyWriteMaster,
phyWriteSlave => phyWriteSlave,
-- I2C AXI-Lite Interfaces (axiClk domain)
i2cReadMaster => i2cReadMaster,
i2cReadSlave => i2cReadSlave,
i2cWriteMaster => i2cWriteMaster,
i2cWriteSlave => i2cWriteSlave,
-- (Optional) Application AXI-Lite Interfaces
appClk => appClk,
appRst => appRst,
Expand Down
5 changes: 3 additions & 2 deletions hardware/XilinxAlveoU55c/pcie-3x16/xdc/XilinxAlveoU55cTiming.xdc
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Original file line number Diff line number Diff line change
Expand Up @@ -8,5 +8,6 @@
## the terms contained in the LICENSE.txt file.
##############################################################################

set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClk0}] -group [get_clocks -include_generated_clocks {qsfp0RefClkP}]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClk0}] -group [get_clocks -include_generated_clocks {qsfp1RefClkP}]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxAlveoU55cPciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks dnaClk]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxAlveoU55cPciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks iprogClk]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxAlveoU55cPciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks -of_objects [get_pins U_axilClk/PllGen.U_Pll/CLKOUT0]
28 changes: 14 additions & 14 deletions hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc
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Expand Up @@ -11,12 +11,12 @@
# HBM Catastrophic Over temperature Output signal to Satellite Controller: active HIGH indicator to Satellite controller to indicate the HBM has exceeds its maximum allowable temperature.
set_property -dict { PACKAGE_PIN BE45 IOSTANDARD LVCMOS18 PULLDOWN TRUE } [get_ports { hbmCatTrip }]

###########
# QSFP[0] #
###########
##########################################
# QSFP[0] - QSFP28 MGTY Interface QUAD 130
##########################################

set_property PACKAGE_PIN AD42 [get_ports { qsfp0RefClkP }] ;# 161.1328125 MHz
set_property PACKAGE_PIN AD43 [get_ports { qsfp0RefClkN }] ;# 161.1328125 MHz
set_property PACKAGE_PIN AD42 [get_ports { qsfp0RefClkP }]
set_property PACKAGE_PIN AD43 [get_ports { qsfp0RefClkN }]

set_property PACKAGE_PIN AD46 [get_ports { qsfp0TxP[0] }]
set_property PACKAGE_PIN AD47 [get_ports { qsfp0TxN[0] }]
Expand All @@ -38,12 +38,12 @@ set_property PACKAGE_PIN AA49 [get_ports { qsfp0TxN[3] }]
set_property PACKAGE_PIN AB51 [get_ports { qsfp0RxP[3] }]
set_property PACKAGE_PIN AB52 [get_ports { qsfp0RxN[3] }]

###########
# QSFP[1] #
###########
##########################################
# QSFP[0] - QSFP28 MGTY Interface QUAD 131
##########################################

set_property PACKAGE_PIN AB42 [get_ports { qsfp1RefClkP }] ;# 161.1328125 MHz
set_property PACKAGE_PIN AB43 [get_ports { qsfp1RefClkN }] ;# 161.1328125 MHz
set_property PACKAGE_PIN AB42 [get_ports { qsfp1RefClkP }]
set_property PACKAGE_PIN AB43 [get_ports { qsfp1RefClkN }]

set_property PACKAGE_PIN AA44 [get_ports { qsfp1TxP[0] }]
set_property PACKAGE_PIN AA45 [get_ports { qsfp1TxN[0] }]
Expand Down Expand Up @@ -73,9 +73,9 @@ set_property PACKAGE_PIN V52 [get_ports { qsfp1RxN[3] }]
create_clock -period 6.206 -name qsfp0RefClkP [get_ports {qsfp0RefClkP}] ;# 161.1328125 MHz
create_clock -period 6.206 -name qsfp1RefClkP [get_ports {qsfp1RefClkP}] ;# 161.1328125 MHz

set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {userClkP}] -group [get_clocks -include_generated_clocks {qsfp0RefClkP}]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {userClkP}] -group [get_clocks -include_generated_clocks {qsfp1RefClkP}]

set_clock_groups -asynchronous \
-group [get_clocks -include_generated_clocks {qsfp0RefClkP}] \
-group [get_clocks -include_generated_clocks {qsfp1RefClkP}]
-group [get_clocks -include_generated_clocks {qsfp1RefClkP}] \
-group [get_clocks -include_generated_clocks {pciRefClk0}] \
-group [get_clocks -include_generated_clocks {pciRefClk1}] \
-group [get_clocks -include_generated_clocks {userClkP}]
17 changes: 12 additions & 5 deletions hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
## the terms contained in the LICENSE.txt file.
##############################################################################

# set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_Core}]
set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {U_Core}]

set_operating_conditions -design_power_budget 63

Expand All @@ -19,6 +19,16 @@ set_operating_conditions -design_power_budget 63
set_property -dict { PACKAGE_PIN BK10 IOSTANDARD LVDS } [get_ports { userClkP }]
set_property -dict { PACKAGE_PIN BL10 IOSTANDARD LVDS } [get_ports { userClkN }]

set_property -dict { PACKAGE_PIN BK43 IOSTANDARD LVDS } [get_ports { hbmRefClkP }]
set_property -dict { PACKAGE_PIN BK44 IOSTANDARD LVDS } [get_ports { hbmRefClkN }]

set_property -dict { PACKAGE_PIN BM14 IOSTANDARD LVCMOS18 } [get_ports { si5394Scl }]
set_property -dict { PACKAGE_PIN BN14 IOSTANDARD LVCMOS18 } [get_ports { si5394Sda }]
set_property -dict { PACKAGE_PIN BM9 IOSTANDARD LVCMOS18 } [get_ports { si5394IrqL }]
set_property -dict { PACKAGE_PIN BN10 IOSTANDARD LVCMOS18 } [get_ports { si5394LolL }]
set_property -dict { PACKAGE_PIN BM10 IOSTANDARD LVCMOS18 } [get_ports { si5394LosL }]
set_property -dict { PACKAGE_PIN BM8 IOSTANDARD LVCMOS18 } [get_ports { si5394RstL }]

####################
# PCIe Constraints #
####################
Expand Down Expand Up @@ -120,16 +130,13 @@ set_property PULLUP true [get_ports pciRstL]
create_clock -period 10.000 -name pciRefClk0 [get_ports {pciRefClkP[0]}]
create_clock -period 10.000 -name pciRefClk1 [get_ports {pciRefClkP[1]}]
create_clock -period 10.000 -name userClkP [get_ports {userClkP}]
create_clock -period 10.000 -name hbmRefClkP [get_ports {hbmRefClkP}]
create_clock -period 16.000 -name dnaClk [get_pins {U_Core/U_REG/U_Version/GEN_DEVICE_DNA.DeviceDna_1/GEN_ULTRA_SCALE.DeviceDnaUltraScale_Inst/BUFGCE_DIV_Inst/O}]
create_clock -period 16.000 -name iprogClk [get_pins {U_Core/U_REG/U_Version/GEN_ICAP.Iprog_1/GEN_ULTRA_SCALE.IprogUltraScale_Inst/BUFGCE_DIV_Inst/O}]

set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClk0}] -group [get_clocks -include_generated_clocks {userClkP}]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClk1}] -group [get_clocks -include_generated_clocks {userClkP}]

set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxAlveoU55cPciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks dnaClk]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxAlveoU55cPciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks iprogClk]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie4c_ip_i/inst/XilinxAlveoU55cPciePhyGen3x16_pcie4c_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] -group [get_clocks -of_objects [get_pins U_axilClk/PllGen.U_Pll/CLKOUT0]

set_false_path -to [get_pins -hier *sync_reg[0]/D]

set_false_path -from [get_ports {pciRstL}]
Expand Down
38 changes: 0 additions & 38 deletions hardware/XilinxVariumC1100/misc/AxiPciePkg.vhd
View file

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