TODO

Here is an informal list of things that would be nice to get done. Feel free to contribute!

• Add stat information back in (e.g., print out the CPI, leveraging the new uarch counters?).
• Use the newest riscv-test benchmarks, which provide printf (but require syscall support) and dump out the uarch counter state.
• Update the 3-stage to work in Princeton mode.
• Use the riscv-dis binary to provide disassembly support (instead of using Chisel RTL, which is expensive), which is provided by the riscv-isa-run repository.
• Provide a Verilog test-harness, and put the 3-stage on a FPGA.